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| author | Brent Stapleton <brent.stapleton@ettus.com> | 2018-08-28 10:15:48 -0700 |
|---|---|---|
| committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-09-06 15:59:25 -0700 |
| commit | ad0bd0d9151b7ea86eadac45528cfbea16a01f37 (patch) | |
| tree | 3ab0c36c4d374bc8e190f23baa08f5fe81af70e6 /mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py | |
| parent | ec0bf1add38e56381293f7a69f6f02447ed9746d (diff) | |
| download | uhd-ad0bd0d9151b7ea86eadac45528cfbea16a01f37.tar.gz uhd-ad0bd0d9151b7ea86eadac45528cfbea16a01f37.tar.bz2 uhd-ad0bd0d9151b7ea86eadac45528cfbea16a01f37.zip | |
n3xx: Get RFNoC crossbar baseport from FPGA
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py index 0370f6e67..0bfae94e1 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py @@ -176,6 +176,7 @@ class MboardRegsControl(object): MB_SFP1_INFO = 0x002C MB_GPIO_MASTER = 0x0030 MB_GPIO_RADIO_SRC = 0x0034 + MB_XBAR_BASEPORT = 0x0038 # Bitfield locations for the MB_CLOCK_CTRL register. MB_CLOCK_CTRL_PPS_SEL_INT_10 = 0 # pps_sel is one-hot encoded! @@ -412,3 +413,7 @@ class MboardRegsControl(object): .format(sfp0_type, sfp1_type)) return "" + def get_xbar_baseport(self): + "Get the RFNoC crossbar base port" + with self.regs: + return self.peek32(self.MB_XBAR_BASEPORT) |