aboutsummaryrefslogtreecommitdiffstats
path: root/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py
diff options
context:
space:
mode:
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py')
-rw-r--r--mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py5
1 files changed, 5 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py
index 0370f6e67..0bfae94e1 100644
--- a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py
+++ b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py
@@ -176,6 +176,7 @@ class MboardRegsControl(object):
MB_SFP1_INFO = 0x002C
MB_GPIO_MASTER = 0x0030
MB_GPIO_RADIO_SRC = 0x0034
+ MB_XBAR_BASEPORT = 0x0038
# Bitfield locations for the MB_CLOCK_CTRL register.
MB_CLOCK_CTRL_PPS_SEL_INT_10 = 0 # pps_sel is one-hot encoded!
@@ -412,3 +413,7 @@ class MboardRegsControl(object):
.format(sfp0_type, sfp1_type))
return ""
+ def get_xbar_baseport(self):
+ "Get the RFNoC crossbar base port"
+ with self.regs:
+ return self.peek32(self.MB_XBAR_BASEPORT)