From ad0bd0d9151b7ea86eadac45528cfbea16a01f37 Mon Sep 17 00:00:00 2001 From: Brent Stapleton Date: Tue, 28 Aug 2018 10:15:48 -0700 Subject: n3xx: Get RFNoC crossbar baseport from FPGA --- mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py') diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py index 0370f6e67..0bfae94e1 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py @@ -176,6 +176,7 @@ class MboardRegsControl(object): MB_SFP1_INFO = 0x002C MB_GPIO_MASTER = 0x0030 MB_GPIO_RADIO_SRC = 0x0034 + MB_XBAR_BASEPORT = 0x0038 # Bitfield locations for the MB_CLOCK_CTRL register. MB_CLOCK_CTRL_PPS_SEL_INT_10 = 0 # pps_sel is one-hot encoded! @@ -412,3 +413,7 @@ class MboardRegsControl(object): .format(sfp0_type, sfp1_type)) return "" + def get_xbar_baseport(self): + "Get the RFNoC crossbar base port" + with self.regs: + return self.peek32(self.MB_XBAR_BASEPORT) -- cgit v1.2.3