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path: root/host/lib/usrp/x300/x300_clock_ctrl.cpp
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* x300: New mode to configure master clock rateScott Torborg2018-11-161-2/+95
| | | | | | | | Add a new clocking mode to automatically configure arbitrary master clock rates. Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com>
* X300: Add support for 11.52 MHz and 23.04 MHz referencesMichael West2018-07-171-12/+82
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* uhd: Update license headersMartin Braun2018-02-191-1/+2
| | | | | | | All copyright is now attributed to "Ettus Research, a National Instruments company". SPDX headers were also updated to latest version 3.0.
* Move all license headers to SPDX format.Martin Braun2017-12-221-12/+1
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* utils: introduce new logging API and remove msg APIAndrej Rode2017-02-201-3/+2
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* Remove all boost:: namespace prefix for uint32_t, int32_t etc. (fixed-width ↵Martin Braun2016-11-081-21/+21
| | | | | | | | types) - Also removes all references to boost/cstdint.hpp and replaces it with stdint.h (The 'correct' replacement would be <cstdint>, but not all of our compilers support that).
* UBX: Phase synchronizationmichael-west2016-02-181-3/+6
| | | | | | | - Disabled MAX2871 VCO auto selection for phase sync - Added checks for new phase sync constraints recently published by Maxim - Added dboard_clock_rate option for X300 - Adjusted timing of SYNC signal relative to dboard referenc clock
* x300: Updated FPGA->ADC Clock delays for all boardsAshish Chaudhari2015-07-241-2/+2
| | | | - Delays changed after ADC config change and FPGA fixes
* Revert "x300: Changed ADC clock swing to 1.6V from 0.7V"Ashish Chaudhari2015-07-231-2/+2
| | | | This reverts commit a12b24027fe1af9ca51949f6a9333ac5451690ef.
* x300: Changed ADC clock swing to 1.6V from 0.7VAshish Chaudhari2015-07-221-2/+2
| | | | - This changed with the ADS62P44 -> ADS62P48 design change
* x300: Updated pre-rev7 board delays after characterizationAshish Chaudhari2015-07-141-3/+2
| | | | - Characterized over process and temperature
* x300: Fixed Windows build issue in x300_clock_ctrlAshish Chaudhari2015-07-091-3/+4
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* x300: Added FPGA->ADC Clock delay for rev 7+ boardsAshish Chaudhari2015-07-071-1/+1
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* x300: Added set/get_clock_delay to x300_clock_ctrlAshish Chaudhari2015-07-011-16/+227
| | | | | | | - This function allows delaying divider pairs using the digital and analog delay blocks in the LMK divider - ctrl object caches delay for later retrieval - Minor fixes to LMK regmap
* Merge branch 'maint'Martin Braun2015-06-091-16/+28
|\ | | | | | | | | | | | | Conflicts: host/lib/usrp/common/ad9361_ctrl.hpp host/lib/usrp/common/ad9361_driver/ad9361_device.h host/lib/usrp/e300/e300_remote_codec_ctrl.hpp
| * x300: Updated clock rate / ref freq warnings for clarityMartin Braun2015-05-221-16/+28
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* | Merge branch 'master' into vivadoAshish Chaudhari2015-04-211-330/+437
|\| | | | | | | | | Conflicts: host/lib/usrp/x300/x300_clock_ctrl.cpp
| * X300: Change dboard clock rate to 50 MHzmichael-west2015-04-101-325/+432
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* | Merge branch 'master' into vivadoAshish Chaudhari2015-04-091-1/+1
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| * x300: Fix for Bug #714: Phase wobble across four channels on two devicesNeel Pandeya2015-03-301-1/+1
| | | | | | | | - Increased filter loop bandwith on clock control chip
* | x300: Timing changes for the new DAC data interfaceAshish Chaudhari2015-03-121-1/+6
|/ | | | | | | | | - Switched DAC to DCI delay bypass mode because we shift the DCI in the FPGA now - Changed LMK control to add 900ps delay to DAC clocks to be consistent with the radio_clk delay. The timing analyzer is expecting the two clocks to have a 0 deg phase diff.
* x300: Cleaned up DAC ctrl and clock init logicAshish Chaudhari2014-11-061-1/+0
| | | | | | | | | | | - DAC: Squashed configuration into 2 main operations: reset and reset_and_resync - DAC: Put in sleep mode during configuration - DAC: Synchronize only if streaming to more than one DAC - DAC: Use falling edge sync mode - DAC: Fixed power up/down settings - DAC: Frontend sync failure is fatal - Clocks: Refactored clock source change logic - Clocks: Cleaned up init and lock-check sequence
* Merge branch 'maint'Martin Braun2014-09-251-5/+0
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| * x300: Reverted back to no analog delay for DAC ref clocksmichael-west2014-09-251-5/+0
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* | Merge branch 'maint'Martin Braun2014-09-241-0/+1
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| * x300: Added output sync for DAC reference clocksMartin Braun2014-09-241-0/+1
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* | Added missing pure virtual destructors to base classesNicholas Corgan2014-09-011-0/+4
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* Changed analog delay on DAC reference and radio clocks from 1075ps to 900psmichael-west2014-08-181-4/+4
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* - Fixes for channel alignmentmichael-west2014-08-181-0/+11
| | | | | | | | | | - Added analog delay for radio clock - Added analog delay for DAC reference clocks - Removed resetting of clock control - Removed setting of reference clock and PPS to external sources during initialization - Fixes for set_time_unknown_pps - Removed wait for PPS edge after setting time from GPSDO - Changed set_time_unknonw_pps to time out based on system time rather than device VITA time
* Addressed comments from review.michael-west2014-03-151-1/+1
| | | | | | - Fixed typos. - Renamed reset() to reset_clocks(). - Created wait_for_ref_locked() function.
* Fixed bug found during testing where internal clock reference was taking ↵Michael West2014-02-201-0/+4
| | | | | | several seconds to lock. Added reset to the clock control and called it whenever the clock reference is changed.
* Pushing the bulk of UHD-3.7.0 code.Ben Hilburn2014-02-141-2/+4
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* Merging USRP X300 and X310 support!!Ben Hilburn2014-02-041-0/+396
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