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| author | Michael West <michael.west@ettus.com> | 2014-02-20 11:27:57 -0800 |
|---|---|---|
| committer | Michael West <michael.west@ettus.com> | 2014-02-20 11:27:57 -0800 |
| commit | 9ccd93ab11ebf2338b763a86aaf740c710fcc13d (patch) | |
| tree | 1227a38aa777b6c58a3ce283ed99b13c39b0ad31 /host/lib/usrp/x300/x300_clock_ctrl.cpp | |
| parent | 4d9c03d44b02d0ee91355280dbc58d1f19deddea (diff) | |
| download | uhd-9ccd93ab11ebf2338b763a86aaf740c710fcc13d.tar.gz uhd-9ccd93ab11ebf2338b763a86aaf740c710fcc13d.tar.bz2 uhd-9ccd93ab11ebf2338b763a86aaf740c710fcc13d.zip | |
Fixed bug found during testing where internal clock reference was taking several seconds to lock.
Added reset to the clock control and called it whenever the clock reference is changed.
Diffstat (limited to 'host/lib/usrp/x300/x300_clock_ctrl.cpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index a986928a7..6a0b19c8c 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -48,6 +48,10 @@ x300_clock_ctrl_impl(uhd::spi_iface::sptr spiface, set_master_clock_rate(master_clock_rate); } +void reset() { + set_master_clock_rate(_master_clock_rate); +} + void sync_clocks(void) { //soft sync: //put the sync IO into output mode - FPGA must be input |