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authorMartin Braun <martin.braun@ettus.com>2014-09-25 17:29:43 -0700
committerMartin Braun <martin.braun@ettus.com>2014-09-25 17:29:43 -0700
commit994e993893d921c074ce4097632f8fa5bdecff66 (patch)
treec1e0fe3601e0ce8d7fa3690f578d0f341e610fed /host/lib/usrp/x300/x300_clock_ctrl.cpp
parenta1767ede3c147c1748c6a33a52469d0cba644bf5 (diff)
parent9dc96fd9bf8d430a9f41f3476bc62cc3ba43e1d7 (diff)
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Merge branch 'maint'
Diffstat (limited to 'host/lib/usrp/x300/x300_clock_ctrl.cpp')
-rw-r--r--host/lib/usrp/x300/x300_clock_ctrl.cpp5
1 files changed, 0 insertions, 5 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp
index ffb97e147..21411e651 100644
--- a/host/lib/usrp/x300/x300_clock_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp
@@ -299,8 +299,6 @@ void set_master_clock_rate(double clock_rate) {
// Register 3
_lmk04816_regs.CLKout6_7_DIV = vco_div;
_lmk04816_regs.CLKout6_7_OSCin_Sel = lmk04816_regs_t::CLKOUT6_7_OSCIN_SEL_VCO;
- _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_EV_X;
- _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_EV_X;
// Register 4
_lmk04816_regs.CLKout8_9_DIV = vco_div;
// Register 5
@@ -322,9 +320,6 @@ void set_master_clock_rate(double clock_rate) {
_lmk04816_regs.CLKout6_TYPE = lmk04816_regs_t::CLKOUT6_TYPE_LVPECL_700MVPP; //DB0_DAC
_lmk04816_regs.CLKout7_TYPE = lmk04816_regs_t::CLKOUT7_TYPE_LVPECL_700MVPP; //DB1_DAC
_lmk04816_regs.CLKout8_TYPE = lmk04816_regs_t::CLKOUT8_TYPE_LVPECL_700MVPP; //DB0_ADC
- // Analog delay of 900ps to synchronize the DAC reference clocks with the source synchronous DAC clocks.
- // This delay may need to vary due to temperature. Tested and verified at room temperature only.
- _lmk04816_regs.CLKout6_7_ADLY = 0x10;
// Register 8
_lmk04816_regs.CLKout9_TYPE = lmk04816_regs_t::CLKOUT9_TYPE_LVPECL_700MVPP; //DB1_ADC