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| author | Brent Stapleton <brent.stapleton@ettus.com> | 2018-08-28 10:15:08 -0700 |
|---|---|---|
| committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-09-06 15:59:25 -0700 |
| commit | ec0bf1add38e56381293f7a69f6f02447ed9746d (patch) | |
| tree | ced4af6c2558fdf7d6644c24abcc2a1df761d275 /mpm/python/usrp_mpm/periph_manager/e320_periphs.py | |
| parent | 77631f36033c774d5b253d9c8ce8d5cbce569182 (diff) | |
| download | uhd-ec0bf1add38e56381293f7a69f6f02447ed9746d.tar.gz uhd-ec0bf1add38e56381293f7a69f6f02447ed9746d.tar.bz2 uhd-ec0bf1add38e56381293f7a69f6f02447ed9746d.zip | |
e320: Get RFNoC crossbar baseport from FPGA
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/e320_periphs.py')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e320_periphs.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py index 4a5ee236a..f5c82c0dd 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py @@ -66,6 +66,7 @@ class MboardRegsControl(object): MB_GPS_STATUS = 0x003C MB_DBOARD_CTRL = 0x0040 MB_DBOARD_STATUS = 0x0044 + MB_XBAR_BASEPORT = 0x0048 # Bitfield locations for the MB_CLOCK_CTRL register. MB_CLOCK_CTRL_PPS_SEL_INT = 0 @@ -409,3 +410,8 @@ class MboardRegsControl(object): else: self.log.trace("RX RF PLL locked") return locked + + def get_xbar_baseport(self): + "Get the RFNoC crossbar base port" + with self.regs: + return self.peek32(self.MB_XBAR_BASEPORT) |