From ec0bf1add38e56381293f7a69f6f02447ed9746d Mon Sep 17 00:00:00 2001 From: Brent Stapleton Date: Tue, 28 Aug 2018 10:15:08 -0700 Subject: e320: Get RFNoC crossbar baseport from FPGA --- mpm/python/usrp_mpm/periph_manager/e320_periphs.py | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'mpm/python/usrp_mpm/periph_manager/e320_periphs.py') diff --git a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py index 4a5ee236a..f5c82c0dd 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py +++ b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py @@ -66,6 +66,7 @@ class MboardRegsControl(object): MB_GPS_STATUS = 0x003C MB_DBOARD_CTRL = 0x0040 MB_DBOARD_STATUS = 0x0044 + MB_XBAR_BASEPORT = 0x0048 # Bitfield locations for the MB_CLOCK_CTRL register. MB_CLOCK_CTRL_PPS_SEL_INT = 0 @@ -409,3 +410,8 @@ class MboardRegsControl(object): else: self.log.trace("RX RF PLL locked") return locked + + def get_xbar_baseport(self): + "Get the RFNoC crossbar base port" + with self.regs: + return self.peek32(self.MB_XBAR_BASEPORT) -- cgit v1.2.3