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| author | Trung Tran <trung.tran@ettus.com> | 2019-01-31 18:36:31 -0800 |
|---|---|---|
| committer | Ashish Chaudhari <ashish.chaudhari@ettus.com> | 2019-02-01 15:28:35 -0800 |
| commit | 3fb8cfe96c293e892a02a94c5c2e51e8d2705791 (patch) | |
| tree | 069914e09077bf39243d3e831dbd6e498e1df710 /mpm/python/usrp_mpm/periph_manager/e320.py | |
| parent | 045bee8abcc371724dd062f527ec36cccb6c187b (diff) | |
| download | uhd-3fb8cfe96c293e892a02a94c5c2e51e8d2705791.tar.gz uhd-3fb8cfe96c293e892a02a94c5c2e51e8d2705791.tar.bz2 uhd-3fb8cfe96c293e892a02a94c5c2e51e8d2705791.zip | |
n3xx: init peripherals before loading FPGA
Issue: Current code loads FPGA too early while many
essential peripherals such as net clocks are not brought up.
This change will make sure those are got init before FPGA loaded.
Signed-off-by: Trung Tran<trung.tran@ettus.com>
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/e320.py')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/e320.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/e320.py b/mpm/python/usrp_mpm/periph_manager/e320.py index d60b7c110..dbcaead2a 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320.py +++ b/mpm/python/usrp_mpm/periph_manager/e320.py @@ -128,7 +128,9 @@ class e320(ZynqComponents, PeriphManagerBase): # Ctor and device initialization tasks ########################################################################### def __init__(self, args): - super(e320, self).__init__(args) + super(e320, self).__init__() + self.overlay_apply() + self.init_dboards(args) if not self._device_initialized: # Don't try and figure out what's going on. Just give up. return |