From 3fb8cfe96c293e892a02a94c5c2e51e8d2705791 Mon Sep 17 00:00:00 2001 From: Trung Tran Date: Thu, 31 Jan 2019 18:36:31 -0800 Subject: n3xx: init peripherals before loading FPGA Issue: Current code loads FPGA too early while many essential peripherals such as net clocks are not brought up. This change will make sure those are got init before FPGA loaded. Signed-off-by: Trung Tran --- mpm/python/usrp_mpm/periph_manager/e320.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'mpm/python/usrp_mpm/periph_manager/e320.py') diff --git a/mpm/python/usrp_mpm/periph_manager/e320.py b/mpm/python/usrp_mpm/periph_manager/e320.py index d60b7c110..dbcaead2a 100644 --- a/mpm/python/usrp_mpm/periph_manager/e320.py +++ b/mpm/python/usrp_mpm/periph_manager/e320.py @@ -128,7 +128,9 @@ class e320(ZynqComponents, PeriphManagerBase): # Ctor and device initialization tasks ########################################################################### def __init__(self, args): - super(e320, self).__init__(args) + super(e320, self).__init__() + self.overlay_apply() + self.init_dboards(args) if not self._device_initialized: # Don't try and figure out what's going on. Just give up. return -- cgit v1.2.3