mpm: Implement 32 bit register interface with SPI

Implement SPI transfers which are 12 bytes in length to support
access for 32 bit register interfaces. 12 byte transactions are
necessary for Titanium MB PS CPLD SPI transactions. This implementation
supports 48 bits of TX data per transfer and offsets all flags and
data shifts from the end of the TX data portion of the transfer buffer
rather than the end of the entire transfer buffer.

1 files changed, 32 insertions, 0 deletions

diff --git a/mpm/lib/spi/spidev_iface.cpp b/mpm/lib/spi/spidev_iface.cpp
index c8a2133e8..c706725b8 100644
--- a/mpm/lib/spi/spidev_iface.cpp
+++ b/mpm/lib/spi/spidev_iface.cpp
@@ -79,6 +79,38 @@ public:
         return uint32_t(rx[1] << 8 | rx[2]);
     }
 
+    uint64_t transfer64_40(const uint64_t data_)
+    {
+        uint64_t data    = data_;
+        uint8_t* tx_data = reinterpret_cast<uint8_t*>(&data);
+
+        // Create tx and rx buffers:
+        /* Address and TX data only represents up to 6 out of 8 bytes to
+           transfer. The remaining bytes are buffer for processing gap
+           and response status. */
+        uint8_t tx[] = {tx_data[5],
+            tx_data[4],
+            tx_data[3],
+            tx_data[2],
+            tx_data[1],
+            tx_data[0],
+            0,
+            0};
+        uint8_t rx[8]; // Buffer length must match tx buffer
+
+        if (transfer(_fd, &tx[0], &rx[0], 8, _speed, _bits, _delay) != 0) {
+            throw mpm::runtime_error(str(boost::format("SPI Transaction failed!")));
+        }
+
+        uint64_t result = rx[3];
+        result = (result << 8) | rx[4];
+        result = (result << 8) | rx[5];
+        result = (result << 8) | rx[6];
+        result = (result << 8) | rx[7];
+
+        return result;
+    }
+
 private:
     int _fd;
     const uint32_t _mode;