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| author | Josh Blum <josh@joshknows.com> | 2010-11-08 17:22:37 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-08 17:22:37 -0800 |
| commit | 81c9f77306dc82f250bfb2871b8bd7db67a40085 (patch) | |
| tree | b1f1ec0a6feb4d66aaa35be97ffa795b122b3673 /host/lib/usrp/usrp2/usrp2_regs.hpp | |
| parent | 374f6ff05e66d10830a7567d2d793de2bf77c06b (diff) | |
| download | uhd-81c9f77306dc82f250bfb2871b8bd7db67a40085.tar.gz uhd-81c9f77306dc82f250bfb2871b8bd7db67a40085.tar.bz2 uhd-81c9f77306dc82f250bfb2871b8bd7db67a40085.zip | |
usrp2: implemented clear state for RX and TX control, and zero sample command support
Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp')
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index c3a4d22de..cef7cf2e6 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -179,7 +179,7 @@ #define U2_REG_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1) #define U2_REG_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2) -#define U2_REG_RX_CTRL_CLEAR_OVERRUN _SR_ADDR(SR_RX_CTRL + 3) // write anything to clear overrun +#define U2_REG_RX_CTRL_CLEAR_STATE _SR_ADDR(SR_RX_CTRL + 3) #define U2_REG_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter #define U2_REG_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet. #define U2_REG_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6) |