From 81c9f77306dc82f250bfb2871b8bd7db67a40085 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 8 Nov 2010 17:22:37 -0800 Subject: usrp2: implemented clear state for RX and TX control, and zero sample command support --- host/lib/usrp/usrp2/usrp2_regs.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp') diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index c3a4d22de..cef7cf2e6 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -179,7 +179,7 @@ #define U2_REG_RX_CTRL_TIME_SECS _SR_ADDR(SR_RX_CTRL + 1) #define U2_REG_RX_CTRL_TIME_TICKS _SR_ADDR(SR_RX_CTRL + 2) -#define U2_REG_RX_CTRL_CLEAR_OVERRUN _SR_ADDR(SR_RX_CTRL + 3) // write anything to clear overrun +#define U2_REG_RX_CTRL_CLEAR_STATE _SR_ADDR(SR_RX_CTRL + 3) #define U2_REG_RX_CTRL_VRT_HEADER _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet. FPGA fills in packet counter #define U2_REG_RX_CTRL_VRT_STREAM_ID _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet. #define U2_REG_RX_CTRL_VRT_TRAILER _SR_ADDR(SR_RX_CTRL + 6) -- cgit v1.2.3