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| author | Josh Blum <josh@joshknows.com> | 2010-05-24 16:31:23 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-05-24 16:31:23 -0700 |
| commit | 39943a5b0c3c210babfd6e62711ea4bf3133866b (patch) | |
| tree | 1380a4d28f55742c7e654bc585988ee45afec2c8 /host/lib/usrp/usrp2/usrp2_regs.hpp | |
| parent | 71169b8e030d984220eadde83c4b40481f97cf6b (diff) | |
| download | uhd-39943a5b0c3c210babfd6e62711ea4bf3133866b.tar.gz uhd-39943a5b0c3c210babfd6e62711ea4bf3133866b.tar.bz2 uhd-39943a5b0c3c210babfd6e62711ea4bf3133866b.zip | |
Added support to set GPIO pins from dboard interface:
write gpio and set pin control (atr or gpio)
Added property to get dboard interface from the dboard obj.
Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp')
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index feeccaa34..0f675357b 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -204,7 +204,7 @@ #define FR_GPIO_RX_SEL FR_GPIO_BASE + 12 // 16 2-bit fields select which source goes to RX DB // each 2-bit sel field is layed out this way -#define FRF_GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define FRF_GPIO_SEL_GPIO 0 // if pin is an output, set by GPIO register #define FRF_GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic #define FRF_GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric #define FRF_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric |