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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-08-01 16:29:34 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-08-01 16:29:34 -0700 |
| commit | db6f3a2d7aabdd0eaa1021ac174edd3cbb77be55 (patch) | |
| tree | a46e395a5700fda1a367ec34b640312b4ff48e3f /host/lib/usrp/b200/b200_regs.hpp | |
| parent | ef5abde4f0c5ef5a16dc7b8ec7a8a5f611a9418f (diff) | |
| download | uhd-db6f3a2d7aabdd0eaa1021ac174edd3cbb77be55.tar.gz uhd-db6f3a2d7aabdd0eaa1021ac174edd3cbb77be55.tar.bz2 uhd-db6f3a2d7aabdd0eaa1021ac174edd3cbb77be55.zip | |
b200: Added variable rate SPI core for AD9361 and ADF4001
- Added b200_local_spi core that adjusts the divider when talking to the two chips
- AD9361 rate is 1MHz and ADF4001 rate is 10kHz
Diffstat (limited to 'host/lib/usrp/b200/b200_regs.hpp')
| -rw-r--r-- | host/lib/usrp/b200/b200_regs.hpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/host/lib/usrp/b200/b200_regs.hpp b/host/lib/usrp/b200/b200_regs.hpp index 2f4373409..dc8a6b0dc 100644 --- a/host/lib/usrp/b200/b200_regs.hpp +++ b/host/lib/usrp/b200/b200_regs.hpp @@ -54,6 +54,7 @@ localparam RB64_CODEC_READBACK = 24; //pll constants static const int AD9361_SLAVENO = (1 << 0); static const int ADF4001_SLAVENO = (1 << 1); +static const double AD9361_SPI_RATE = 1e6; static const double ADF4001_SPI_RATE = 10e3; //slow for large time constant on spi lines /* ATR Control Bits */ |