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| author | Max Köhler <max.koehler@ni.com> | 2021-02-05 13:14:41 -0600 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-10 11:56:58 -0500 |
| commit | 7015f5ed2d495f3908773b7c7d74864d0cc3871a (patch) | |
| tree | e9c9f7d95f5c35c089bfc9534707934bfe41344a /fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc | |
| parent | 6d3765605262016a80f71e36357f749ea35cbe5a (diff) | |
| download | uhd-7015f5ed2d495f3908773b7c7d74864d0cc3871a.tar.gz uhd-7015f5ed2d495f3908773b7c7d74864d0cc3871a.tar.bz2 uhd-7015f5ed2d495f3908773b7c7d74864d0cc3871a.zip | |
fpga: x400: cpld: Add support for X410 motherboard CPLD
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Diffstat (limited to 'fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc')
| -rw-r--r-- | fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc b/fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc new file mode 100644 index 000000000..21935c2e7 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc @@ -0,0 +1,20 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# +# Timing constants for the MB CPLD <-> DB CPLD SPI interface +# + +# Delays are rounded to integer values which leave a slack of >1ns on each setup +# and hold path without requirement for adding hold delays (as reported +# by Quartus fitter report). +# The signal might change before the SCLK edge as the internal +# registers are driven by PLL reference clock rather than the SPI clock used +# for the port timing constaints. +set db_cpld_spi_max_out 14.000 +set db_cpld_spi_min_out 2.000 +set db_cpld_spi_max_in 2.000 +set db_cpld_spi_min_in -2.000 |