From 7015f5ed2d495f3908773b7c7d74864d0cc3871a Mon Sep 17 00:00:00 2001 From: Max Köhler Date: Fri, 5 Feb 2021 13:14:41 -0600 Subject: fpga: x400: cpld: Add support for X410 motherboard CPLD Co-authored-by: Humberto Jimenez Co-authored-by: Javier Valenzuela --- fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc (limited to 'fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc') diff --git a/fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc b/fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc new file mode 100644 index 000000000..21935c2e7 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc @@ -0,0 +1,20 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# +# Timing constants for the MB CPLD <-> DB CPLD SPI interface +# + +# Delays are rounded to integer values which leave a slack of >1ns on each setup +# and hold path without requirement for adding hold delays (as reported +# by Quartus fitter report). +# The signal might change before the SCLK edge as the internal +# registers are driven by PLL reference clock rather than the SPI clock used +# for the port timing constaints. +set db_cpld_spi_max_out 14.000 +set db_cpld_spi_min_out 2.000 +set db_cpld_spi_max_in 2.000 +set db_cpld_spi_min_in -2.000 -- cgit v1.2.3