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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
| commit | ff1546f8137f7f92bb250f685561b0c34cc0e053 (patch) | |
| tree | 7fa6fd05c8828df256a1b20e2935bd3ba9899e2c /fpga/usrp3/lib/zynq_fifo/Makefile.srcs | |
| parent | 4f691d88123784c2b405816925f1a1aef69d18c1 (diff) | |
| download | uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.gz uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.bz2 uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.zip | |
Pushing the bulk of UHD-3.7.0 code.
Diffstat (limited to 'fpga/usrp3/lib/zynq_fifo/Makefile.srcs')
| -rw-r--r-- | fpga/usrp3/lib/zynq_fifo/Makefile.srcs | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/zynq_fifo/Makefile.srcs b/fpga/usrp3/lib/zynq_fifo/Makefile.srcs new file mode 100644 index 000000000..0a63d1627 --- /dev/null +++ b/fpga/usrp3/lib/zynq_fifo/Makefile.srcs @@ -0,0 +1,15 @@ +# +# Copyright 2012 Ettus Research LLC +# + +################################################## +# ZYNQ FIFO interface sources +################################################## +ZYNQ_FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/zynq_fifo/, \ +zf_arbiter.v \ +zf_stream_to_host.v \ +zf_host_to_stream.v \ +zf_slave_readback.v \ +zf_slave_settings.v \ +zynq_fifo_top.v \ +)) |