From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Fri, 14 Feb 2014 12:05:07 -0800
Subject: Pushing the bulk of UHD-3.7.0 code.

---
 fpga/usrp3/lib/zynq_fifo/Makefile.srcs | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 fpga/usrp3/lib/zynq_fifo/Makefile.srcs

(limited to 'fpga/usrp3/lib/zynq_fifo/Makefile.srcs')

diff --git a/fpga/usrp3/lib/zynq_fifo/Makefile.srcs b/fpga/usrp3/lib/zynq_fifo/Makefile.srcs
new file mode 100644
index 000000000..0a63d1627
--- /dev/null
+++ b/fpga/usrp3/lib/zynq_fifo/Makefile.srcs
@@ -0,0 +1,15 @@
+#
+# Copyright 2012 Ettus Research LLC
+#
+
+##################################################
+# ZYNQ FIFO interface sources
+##################################################
+ZYNQ_FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/zynq_fifo/, \
+zf_arbiter.v \
+zf_stream_to_host.v \
+zf_host_to_stream.v \
+zf_slave_readback.v \
+zf_slave_settings.v \
+zynq_fifo_top.v \
+))
-- 
cgit v1.2.3