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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
| commit | 0df4b801a34697f2058b4a7b95e08d2a0576c9db (patch) | |
| tree | be10e78d1a97c037a9e7492360a178d1873b9c09 /fpga/usrp2/coregen/coregen_s6.cgp | |
| parent | 6e7bc850b66e8188718248b76b729c7cf9c89700 (diff) | |
| download | uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.gz uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.bz2 uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.zip | |
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Diffstat (limited to 'fpga/usrp2/coregen/coregen_s6.cgp')
| -rw-r--r-- | fpga/usrp2/coregen/coregen_s6.cgp | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/fpga/usrp2/coregen/coregen_s6.cgp b/fpga/usrp2/coregen/coregen_s6.cgp new file mode 100644 index 000000000..1abd1b021 --- /dev/null +++ b/fpga/usrp2/coregen/coregen_s6.cgp @@ -0,0 +1,22 @@ +# Date: Fri May 4 20:42:23 2012 + +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx75 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg484 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = ./tmp/ + +# CRC: f7d4ca66 |