From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Thu, 10 Oct 2013 10:17:27 -0700
Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt
 Ettus.

---
 fpga/usrp2/coregen/coregen_s6.cgp | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 fpga/usrp2/coregen/coregen_s6.cgp

(limited to 'fpga/usrp2/coregen/coregen_s6.cgp')

diff --git a/fpga/usrp2/coregen/coregen_s6.cgp b/fpga/usrp2/coregen/coregen_s6.cgp
new file mode 100644
index 000000000..1abd1b021
--- /dev/null
+++ b/fpga/usrp2/coregen/coregen_s6.cgp
@@ -0,0 +1,22 @@
+# Date: Fri May  4 20:42:23 2012
+
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx75
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+SET workingdirectory = ./tmp/
+
+# CRC: f7d4ca66
-- 
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