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author | Josh Blum <josh@joshknows.com> | 2010-06-18 12:33:40 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-06-18 12:33:40 -0700 |
commit | efbeb60d1dd7e870a48cf42df9a3650aefbf26cd (patch) | |
tree | 12131942ff9f85f7776a864cb79120bab778d8f9 /fpga/usrp2/control_lib/setting_reg.v | |
parent | df80be9c61d95402976d3349acf62630044c1939 (diff) | |
parent | edcc2df10ba59ed91ac9513c2dc1d36e155caaec (diff) | |
download | uhd-efbeb60d1dd7e870a48cf42df9a3650aefbf26cd.tar.gz uhd-efbeb60d1dd7e870a48cf42df9a3650aefbf26cd.tar.bz2 uhd-efbeb60d1dd7e870a48cf42df9a3650aefbf26cd.zip |
Merge branch 'uhd_fpga_merge' into pre_merge
Diffstat (limited to 'fpga/usrp2/control_lib/setting_reg.v')
-rw-r--r-- | fpga/usrp2/control_lib/setting_reg.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/fpga/usrp2/control_lib/setting_reg.v b/fpga/usrp2/control_lib/setting_reg.v index c8aff230f..3d3bb65e5 100644 --- a/fpga/usrp2/control_lib/setting_reg.v +++ b/fpga/usrp2/control_lib/setting_reg.v @@ -1,9 +1,11 @@ module setting_reg - #(parameter my_addr = 0, parameter at_reset=32'd0) + #(parameter my_addr = 0, + parameter width = 32, + parameter at_reset=32'd0) (input clk, input rst, input strobe, input wire [7:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); + input wire [31:0] in, output reg [width-1:0] out, output reg changed); always @(posedge clk) if(rst) |