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author | Josh Blum <josh@joshknows.com> | 2010-06-15 18:24:33 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-06-15 18:24:33 -0700 |
commit | edcc2df10ba59ed91ac9513c2dc1d36e155caaec (patch) | |
tree | 1a1ec2c0b5500990c991c27af03dbe48c10ce7ca /fpga/usrp2/control_lib/setting_reg.v | |
parent | a89d684ba2b81c6e18d348965dffb919edb56fea (diff) | |
parent | 9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 (diff) | |
download | uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.gz uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.bz2 uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.zip |
Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_master
Conflicts:
fpga/.gitignore
Diffstat (limited to 'fpga/usrp2/control_lib/setting_reg.v')
-rw-r--r-- | fpga/usrp2/control_lib/setting_reg.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/fpga/usrp2/control_lib/setting_reg.v b/fpga/usrp2/control_lib/setting_reg.v index c8aff230f..3d3bb65e5 100644 --- a/fpga/usrp2/control_lib/setting_reg.v +++ b/fpga/usrp2/control_lib/setting_reg.v @@ -1,9 +1,11 @@ module setting_reg - #(parameter my_addr = 0, parameter at_reset=32'd0) + #(parameter my_addr = 0, + parameter width = 32, + parameter at_reset=32'd0) (input clk, input rst, input strobe, input wire [7:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); + input wire [31:0] in, output reg [width-1:0] out, output reg changed); always @(posedge clk) if(rst) |