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#!/bin/sh
rm -rf isim*
rm -rf gen_ddrlvds_tb
rm -rf fuse*
\
# --sourcelibdir ../../models \
vlogcomp \
--sourcelibext .v \
--sourcelibdir ../../coregen \
--sourcelibdir ../../control_lib \
--sourcelibdir . \
--sourcelibdir $XILINX/verilog/src \
--sourcelibdir $XILINX/verilog/src/unisims \
--work work \
gen_ddrlvds_tb.v
fuse -o gen_ddrlvds_tb gen_ddrlvds_tb
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