1 files changed, 34 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/simulator/sim_dboard.py b/mpm/python/usrp_mpm/simulator/sim_dboard.py
index a264eae9c..90f8be724 100644
--- a/mpm/python/usrp_mpm/simulator/sim_dboard.py
+++ b/mpm/python/usrp_mpm/simulator/sim_dboard.py
@@ -7,6 +7,11 @@ from usrp_mpm.dboard_manager import DboardManagerBase
 from usrp_mpm.mpmlog import get_logger
 from usrp_mpm.mpmutils import to_native_str
 
+registry = {}
+
+def register_dboard_class(cls):
+    registry[cls.__name__] = cls
+
 class SimulatedDboardBase(DboardManagerBase):
     """
     A class to simulate daughterboards in a simulated device.
@@ -57,3 +62,32 @@ class SimulatedDboardBase(DboardManagerBase):
                 self.log.debug("Called {} with args: {}".format(prop_name, args))
                 return func(*args)
             setattr(self, prop_name, wrapped_func)
+
+class SimulatedCatalinaDboard(SimulatedDboardBase):
+    pids = [0x0110]
+
+    extra_methods = [
+        ("set_gain", lambda target, gain: gain),
+        ("catalina_tune", lambda which, freq: freq),
+        ("set_bw_filter", lambda which, freq: freq),
+        "set_dc_offset_auto",
+        "set_iq_balance_auto",
+        "set_agc",
+        "set_active_chains",
+        "set_timing_mode",
+        "data_port_loopback"
+    ]
+
+    def __init__(self, slot_idx, clock_rate_cb, **kwargs):
+        super().__init__(slot_idx, **kwargs)
+        self.clock_rate_cb = clock_rate_cb
+        self.master_clock_rate = 122.88e6
+
+    def get_master_clock_rate(self):
+        return self.master_clock_rate
+
+    def set_catalina_clock_rate(self, rate):
+        self.clock_rate_cb(rate)
+        return rate
+
+register_dboard_class(SimulatedCatalinaDboard)