5 files changed, 15 insertions, 15 deletions
diff --git a/host/include/uhd/rfnoc/blocks/ddc_1x64.yml b/host/include/uhd/rfnoc/blocks/ddc_1x64.yml
index 3d21ea527..2ea0af151 100644
--- a/host/include/uhd/rfnoc/blocks/ddc_1x64.yml
+++ b/host/include/uhd/rfnoc/blocks/ddc_1x64.yml
@@ -10,7 +10,7 @@ clocks:
     freq: "[]"
   - name: rfnoc_ctrl
     freq: "[]"
-  - name: ddc
+  - name: ce
     freq: "[]"
 
 control:
@@ -18,7 +18,7 @@ control:
   fpga_iface: ctrlport
   interface_direction: master_slave
   fifo_depth: 32
-  clk_domain: ddc
+  clk_domain: ce
   ctrlport:
     byte_mode: True
     timed: False
@@ -31,7 +31,7 @@ parameters:
 
 data:
   fpga_iface: axis_chdr
-  clk_domain: ddc
+  clk_domain: ce
   mtu: 1024
   inputs:
     port0:
diff --git a/host/include/uhd/rfnoc/blocks/ddc_2x64.yml b/host/include/uhd/rfnoc/blocks/ddc_2x64.yml
index a79a07c8f..ae08ecece 100644
--- a/host/include/uhd/rfnoc/blocks/ddc_2x64.yml
+++ b/host/include/uhd/rfnoc/blocks/ddc_2x64.yml
@@ -10,7 +10,7 @@ clocks:
     freq: "[]"
   - name: rfnoc_ctrl
     freq: "[]"
-  - name: ddc
+  - name: ce
     freq: "[]"
 
 control:
@@ -18,7 +18,7 @@ control:
   fpga_iface: ctrlport
   interface_direction: master_slave
   fifo_depth: 32
-  clk_domain: ddc
+  clk_domain: ce
   ctrlport:
     byte_mode: True
     timed: False
@@ -31,7 +31,7 @@ parameters:
 
 data:
   fpga_iface: axis_chdr
-  clk_domain: ddc
+  clk_domain: ce
   mtu: 1024
   inputs:
     port0:
diff --git a/host/include/uhd/rfnoc/blocks/duc_1x64.yml b/host/include/uhd/rfnoc/blocks/duc_1x64.yml
index 515f426f2..963f576d2 100644
--- a/host/include/uhd/rfnoc/blocks/duc_1x64.yml
+++ b/host/include/uhd/rfnoc/blocks/duc_1x64.yml
@@ -10,7 +10,7 @@ clocks:
     freq: "[]"
   - name: rfnoc_ctrl
     freq: "[]"
-  - name: duc
+  - name: ce
     freq: "[]"
 
 control:
@@ -18,7 +18,7 @@ control:
   fpga_iface: ctrlport
   interface_direction: master_slave
   fifo_depth: 32
-  clk_domain: duc
+  clk_domain: ce
   ctrlport:
     byte_mode: True
     timed: False
@@ -31,7 +31,7 @@ parameters:
 
 data:
   fpga_iface: axis_chdr
-  clk_domain: duc
+  clk_domain: ce
   mtu: 1024
   inputs:
     port0:
diff --git a/host/include/uhd/rfnoc/blocks/duc_2x64.yml b/host/include/uhd/rfnoc/blocks/duc_2x64.yml
index fd8add930..6798ef412 100644
--- a/host/include/uhd/rfnoc/blocks/duc_2x64.yml
+++ b/host/include/uhd/rfnoc/blocks/duc_2x64.yml
@@ -10,7 +10,7 @@ clocks:
     freq: "[]"
   - name: rfnoc_ctrl
     freq: "[]"
-  - name: duc
+  - name: ce
     freq: "[]"
 
 control:
@@ -18,7 +18,7 @@ control:
   fpga_iface: ctrlport
   interface_direction: master_slave
   fifo_depth: 32
-  clk_domain: duc
+  clk_domain: ce
   ctrlport:
     byte_mode: True
     timed: False
@@ -31,7 +31,7 @@ parameters:
 
 data:
   fpga_iface: axis_chdr
-  clk_domain: duc
+  clk_domain: ce
   mtu: 1024
   inputs:
     port0:
diff --git a/host/include/uhd/rfnoc/blocks/fft_1x64.yml b/host/include/uhd/rfnoc/blocks/fft_1x64.yml
index ac2155381..090e4e507 100644
--- a/host/include/uhd/rfnoc/blocks/fft_1x64.yml
+++ b/host/include/uhd/rfnoc/blocks/fft_1x64.yml
@@ -10,7 +10,7 @@ clocks:
     freq: "[]"
   - name: rfnoc_ctrl
     freq: "[]"
-  - name: fft
+  - name: ce
     freq: "[]"
 
 control:
@@ -18,7 +18,7 @@ control:
   fpga_iface: ctrlport
   interface_direction: master_slave
   fifo_depth: 32
-  clk_domain: fft
+  clk_domain: ce
   ctrlport:
     byte_mode: True
     timed: False
@@ -28,7 +28,7 @@ control:
 
 data:
   fpga_iface: axis_chdr
-  clk_domain: fft
+  clk_domain: ce
   mtu: 1024
   inputs:
     port0: