diff options
Diffstat (limited to 'fpga/usrp3/top/n3xx/n310_aurora.xdc')
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_aurora.xdc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/fpga/usrp3/top/n3xx/n310_aurora.xdc b/fpga/usrp3/top/n3xx/n310_aurora.xdc new file mode 100644 index 000000000..1a76687e6 --- /dev/null +++ b/fpga/usrp3/top/n3xx/n310_aurora.xdc @@ -0,0 +1,15 @@ +# +# Copyright 2017 Ettus Research, A National Instruments Company +# SPDX-License-Identifier: LGPL-3.0 +# + + +create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_gen_i/dclk_divide_by_2_buf/O"}] + +set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks aurora_init_clk] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] + +set_false_path -to [get_pins -hierarchical -filter {NAME =~ "qsfp_wrapper_i/lanes[*].lane_i/mgt_io_i/aurora_phy*/aurora_64b66b_pcs_pma*/*/gt_reset_sync/stg1_*_cdc_to_reg/D"}] |