diff options
Diffstat (limited to 'fpga/usrp3/top/e320')
| -rw-r--r-- | fpga/usrp3/top/e320/Makefile.e320.inc | 3 | ||||
| -rw-r--r-- | fpga/usrp3/top/e320/e320.v | 21 | ||||
| -rw-r--r-- | fpga/usrp3/top/e320/e320_core.v | 7 |
3 files changed, 25 insertions, 6 deletions
diff --git a/fpga/usrp3/top/e320/Makefile.e320.inc b/fpga/usrp3/top/e320/Makefile.e320.inc index b8544f3cd..c546b7919 100644 --- a/fpga/usrp3/top/e320/Makefile.e320.inc +++ b/fpga/usrp3/top/e320/Makefile.e320.inc @@ -120,13 +120,14 @@ $(RFNOC_BLOCK_RADIO_SRCS) \ $(abspath $(MB_XDC)) EDGE_TBL_DEF="RFNOC_EDGE_TBL_FILE=$(call RESOLVE_PATH,$(EDGE_FILE))" +IMAGE_CORE_DEF="RFNOC_IMAGE_CORE_HDR=$(call RESOLVE_PATH,$(IMAGE_CORE:.v=.vh))" ################################################## # Dependency Targets ################################################## .SECONDEXPANSION: -VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) +VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(EDGE_TBL_DEF) $(IMAGE_CORE_DEF) # DESIGN_SRCS and VERILOG_DEFS must be defined bin: .prereqs $$(DESIGN_SRCS) ip diff --git a/fpga/usrp3/top/e320/e320.v b/fpga/usrp3/top/e320/e320.v index 501f6a06d..f16d1877f 100644 --- a/fpga/usrp3/top/e320/e320.v +++ b/fpga/usrp3/top/e320/e320.v @@ -175,6 +175,22 @@ module e320 ( ); + // Include the RFNoC image core header file + `ifdef RFNOC_IMAGE_CORE_HDR + `include `"`RFNOC_IMAGE_CORE_HDR`" + `else + ERROR_RFNOC_IMAGE_CORE_HDR_not_defined(); + `define CHDR_WIDTH 64 + `define RFNOC_PROTOVER { 8'd1, 8'd0 } + `endif + localparam CHDR_W = `CHDR_WIDTH; + localparam RFNOC_PROTOVER = `RFNOC_PROTOVER; + + // This USRP currently only supports 64-bit CHDR width + if (CHDR_W != 64) begin : gen_chdr_w_error + CHDR_W_must_be_64_for_this_USRP(); + end + `ifdef SFP_1GBE parameter PROTOCOL = "1GbE"; parameter MDIO_EN = 1'b1; @@ -207,7 +223,6 @@ module e320 ( localparam NUM_CHANNELS_PER_RADIO = 2; localparam NUM_DBOARDS = 1; localparam NUM_CHANNELS = NUM_RADIOS * NUM_CHANNELS_PER_RADIO; - localparam [15:0] RFNOC_PROTOVER = {8'd1, 8'd0}; // Clocks wire xgige_clk156; @@ -1690,7 +1705,9 @@ module e320 ( .NUM_CHANNELS(NUM_CHANNELS), .NUM_DBOARDS(NUM_DBOARDS), .FP_GPIO_WIDTH(FP_GPIO_WIDTH), - .DB_GPIO_WIDTH(DB_GPIO_WIDTH) + .DB_GPIO_WIDTH(DB_GPIO_WIDTH), + .CHDR_W(CHDR_W), + .RFNOC_PROTOVER(RFNOC_PROTOVER) ) e320_core_i ( //Clocks and resets diff --git a/fpga/usrp3/top/e320/e320_core.v b/fpga/usrp3/top/e320/e320_core.v index a63bdda91..a49f28bf1 100644 --- a/fpga/usrp3/top/e320/e320_core.v +++ b/fpga/usrp3/top/e320/e320_core.v @@ -25,7 +25,7 @@ module e320_core #( parameter NUM_CHANNELS_PER_DBOARD = 2, parameter FP_GPIO_WIDTH = 8, // Front panel GPIO width parameter DB_GPIO_WIDTH = 16, // Daughterboard GPIO width - parameter CHDR_WIDTH = 16'd64 , + parameter CHDR_W = 64, parameter RFNOC_PROTOVER = {8'd1, 8'd0} )( // Clocks and resets @@ -468,7 +468,7 @@ module e320_core #( cp_glob_resp_data <= { 16'd0, device_id }; REG_RFNOC_INFO: - cp_glob_resp_data <= {CHDR_WIDTH[15:0], RFNOC_PROTOVER[15:0]}; + cp_glob_resp_data <= {CHDR_W[15:0], RFNOC_PROTOVER[15:0]}; REG_COMPAT_NUM: cp_glob_resp_data <= {COMPAT_MAJOR[15:0], COMPAT_MINOR[15:0]}; @@ -1028,7 +1028,8 @@ module e320_core #( end rfnoc_image_core #( - .PROTOVER(RFNOC_PROTOVER) + .CHDR_W (CHDR_W), + .PROTOVER (RFNOC_PROTOVER) ) rfnoc_sandbox_i ( .chdr_aclk (bus_clk ), .ctrl_aclk (clk40 ), |