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-rw-r--r--fpga/usrp1/sdr_lib/hb/hbd_tb/HBD80
-rw-r--r--fpga/usrp1/sdr_lib/hb/hbd_tb/really_golden142
-rw-r--r--fpga/usrp1/sdr_lib/hb/hbd_tb/regression95
-rwxr-xr-xfpga/usrp1/sdr_lib/hb/hbd_tb/run_hbd4
-rw-r--r--fpga/usrp1/sdr_lib/hb/hbd_tb/test_hbd.v75
5 files changed, 0 insertions, 396 deletions
diff --git a/fpga/usrp1/sdr_lib/hb/hbd_tb/HBD b/fpga/usrp1/sdr_lib/hb/hbd_tb/HBD
deleted file mode 100644
index 574fbba91..000000000
--- a/fpga/usrp1/sdr_lib/hb/hbd_tb/HBD
+++ /dev/null
@@ -1,80 +0,0 @@
-*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-@28
-test_hbd.clock
-test_hbd.reset
-@420
-test_hbd.halfband_decim.middle_data[15:0]
-@22
-test_hbd.halfband_decim.sum_even[33:0]
-test_hbd.halfband_decim.base_addr[3:0]
-@420
-test_hbd.i_in[15:0]
-@24
-test_hbd.halfband_decim.phase[3:0]
-test_hbd.halfband_decim.ram16_even.rd_addr1[3:0]
-test_hbd.halfband_decim.ram16_even.rd_addr2[3:0]
-test_hbd.halfband_decim.ram16_even.wr_addr[3:0]
-test_hbd.halfband_decim.ram16_even.wr_data[15:0]
-@28
-test_hbd.halfband_decim.ram16_even.write
-@420
-test_hbd.halfband_decim.sum[15:0]
-test_hbd.halfband_decim.product[30:0]
-test_hbd.halfband_decim.dout[33:0]
-test_hbd.halfband_decim.sum_even[33:0]
-@22
-test_hbd.halfband_decim.acc.addend[30:0]
-@28
-test_hbd.halfband_decim.acc.reset
-@420
-test_hbd.halfband_decim.acc.sum[33:0]
-test_hbd.halfband_decim.mult.x[15:0]
-test_hbd.halfband_decim.mult.y[15:0]
-@28
-test_hbd.halfband_decim.acc.clear
-test_hbd.strobe_in
-test_hbd.strobe_out
-test_hbd.halfband_decim.acc_en
-@420
-test_hbd.i_out[15:0]
-@28
-test_hbd.halfband_decim.mult_en
-test_hbd.halfband_decim.latch_result
-@420
-test_hbd.halfband_decim.sum[15:0]
-test_hbd.halfband_decim.sum_even[33:0]
-test_hbd.halfband_decim.dout[33:0]
-test_hbd.halfband_decim.data_out[15:0]
-@22
-test_hbd.halfband_decim.data_out[15:0]
-@28
-test_hbd.halfband_decim.dout[33:0]
-@29
-test_hbd.halfband_decim.acc_en
-@22
-test_hbd.halfband_decim.base_addr[3:0]
-@28
-test_hbd.halfband_decim.clear
-test_hbd.halfband_decim.latch_result
-test_hbd.halfband_decim.mult_en
-test_hbd.halfband_decim.mult_en_pre
-@22
-test_hbd.halfband_decim.phase[3:0]
-@28
-test_hbd.halfband_decim.start
-test_hbd.halfband_decim.start_d1
-test_hbd.halfband_decim.start_d2
-test_hbd.halfband_decim.start_d3
-test_hbd.halfband_decim.start_d4
-test_hbd.halfband_decim.start_d5
-test_hbd.halfband_decim.start_d6
-test_hbd.halfband_decim.start_d7
-test_hbd.halfband_decim.start_d8
-test_hbd.halfband_decim.start_d9
-test_hbd.halfband_decim.start_dA
-test_hbd.halfband_decim.start_dB
-test_hbd.halfband_decim.start_dC
-test_hbd.halfband_decim.start_dD
-test_hbd.halfband_decim.store_odd
-test_hbd.halfband_decim.strobe_in
-test_hbd.halfband_decim.strobe_out
diff --git a/fpga/usrp1/sdr_lib/hb/hbd_tb/really_golden b/fpga/usrp1/sdr_lib/hb/hbd_tb/really_golden
deleted file mode 100644
index 2d24a9e14..000000000
--- a/fpga/usrp1/sdr_lib/hb/hbd_tb/really_golden
+++ /dev/null
@@ -1,142 +0,0 @@
-VCD info: dumpfile test_hbd.vcd opened for output.
- x
- x
- x
- x
- x
- x
- x
- x
- x
- x
- x
- x
- x
- x
- x
- x
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 8192
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
- 0
-- 4
- 18
-- 63
- 167
-- 367
- 737
-- 1539
- 5146
- 5146
-- 1539
- 737
-- 367
- 167
-- 63
- 18
-- 4
- 0
- 0
- 0
- 0
- 0
-- 4
- 14
-- 49
- 118
-- 249
- 488
- 7141
-12287
-17433
-15894
-16631
-16264
-16432
-16368
-16387
-16383
-16383
-16383
-16383
-16383
-16387
-16368
-16432
-16264
-16631
-15894
- 9241
- 4095
-- 1051
- 488
-- 249
- 118
-- 49
- 14
-- 4
- 0
- 0
- 0
- 0
- 0
-- 4
- 14
-- 49
- 118
-- 249
- 488
-- 1051
-12287
-17433
-15894
-16631
-16264
-16432
-16368
-16387
-16383
-16383
-16383
-16383
-16383
-16387
-16368
-16432
-16264
-16631
-15894
-17433
- 4095
-- 1051
- 488
-- 249
- 118
-- 49
- 14
-- 4
- 0
- 0
- 0
- 0
diff --git a/fpga/usrp1/sdr_lib/hb/hbd_tb/regression b/fpga/usrp1/sdr_lib/hb/hbd_tb/regression
deleted file mode 100644
index fc279c2f2..000000000
--- a/fpga/usrp1/sdr_lib/hb/hbd_tb/regression
+++ /dev/null
@@ -1,95 +0,0 @@
-echo "Baseline 1000"
-iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v ; ./test_hbd >golden
-diff golden really_golden
-
-echo
-echo "Test 100"
-iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 50"
-iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 40"
-iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 30"
-iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 25"
-iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 20"
-iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 19"
-iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 18"
-iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 17"
-iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 16"
-iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 15"
-iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 14"
-iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 13"
-iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 12"
-iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 11"
-iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 10"
-iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 9"
-iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 8"
-iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 7"
-iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 6"
-iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 5"
-iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 4"
-iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v ; ./test_hbd >output ; diff output golden
-
-echo
-echo "Test 3"
-iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v ; ./test_hbd >output ; diff output golden
diff --git a/fpga/usrp1/sdr_lib/hb/hbd_tb/run_hbd b/fpga/usrp1/sdr_lib/hb/hbd_tb/run_hbd
deleted file mode 100755
index b8aec7574..000000000
--- a/fpga/usrp1/sdr_lib/hb/hbd_tb/run_hbd
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/sh
-
-iverilog -y .. -o test_hbd test_hbd.v
-./test_hbd
diff --git a/fpga/usrp1/sdr_lib/hb/hbd_tb/test_hbd.v b/fpga/usrp1/sdr_lib/hb/hbd_tb/test_hbd.v
deleted file mode 100644
index 01ab5e7e0..000000000
--- a/fpga/usrp1/sdr_lib/hb/hbd_tb/test_hbd.v
+++ /dev/null
@@ -1,75 +0,0 @@
-
-
-module test_hbd();
-
- reg clock;
- initial clock = 1'b0;
- always #5 clock <= ~clock;
-
- reg reset;
- initial reset = 1'b1;
- initial #1000 reset = 1'b0;
-
- initial $dumpfile("test_hbd.vcd");
- initial $dumpvars(0,test_hbd);
-
- reg [15:0] i_in, q_in;
- wire [15:0] i_out, q_out;
-
- reg strobe_in;
- wire strobe_out;
- reg coeff_write;
- reg [15:0] coeff_data;
- reg [4:0] coeff_addr;
-
- halfband_decim halfband_decim
- ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out),
- .data_in(i_in),.data_out(i_out) );
-
- always @(posedge strobe_out)
- if(i_out[15])
- $display("-%d",65536-i_out);
- else
- $display("%d",i_out);
-
- initial
- begin
- strobe_in = 1'b0;
- @(negedge reset);
- @(posedge clock);
- while(1)
- begin
- strobe_in <= #1 1'b1;
- @(posedge clock);
- strobe_in <= #1 1'b0;
- repeat (`RATE)
- @(posedge clock);
- end
- end
-
- initial #10000000 $finish; // Just in case...
-
- initial
- begin
- i_in <= #1 16'd0;
- repeat (40) @(posedge strobe_in);
- i_in <= #1 16'd16384;
- @(posedge strobe_in);
- i_in <= #1 16'd0;
- repeat (40) @(posedge strobe_in);
- i_in <= #1 16'd16384;
- @(posedge strobe_in);
- i_in <= #1 16'd0;
- repeat (40) @(posedge strobe_in);
- i_in <= #1 16'd16384;
- repeat (40) @(posedge strobe_in);
- i_in <= #1 16'd0;
- repeat (41) @(posedge strobe_in);
- i_in <= #1 16'd16384;
- repeat (40) @(posedge strobe_in);
- i_in <= #1 16'd0;
- repeat (40) @(posedge strobe_in);
- repeat (7) @(posedge clock);
- $finish;
- end // initial begin
-endmodule // test_hb
generated by cgit v1.2.3 (git 2.46.0) at 2025-11-04 09:41:53 +0000