diff options
| -rw-r--r-- | firmware/microblaze/apps/txrx.c | 56 | ||||
| -rw-r--r-- | firmware/microblaze/lib/db.h | 3 | ||||
| -rw-r--r-- | firmware/microblaze/lib/db_init.c | 12 | ||||
| -rw-r--r-- | include/uhd/usrp/dboard/interface.hpp | 6 | ||||
| -rw-r--r-- | lib/CMakeLists.txt | 1 | ||||
| -rw-r--r-- | lib/usrp/mboard/usrp2/dboard_interface.cpp | 111 | ||||
| -rw-r--r-- | lib/usrp/mboard/usrp2/dboard_interface.hpp | 24 | ||||
| -rw-r--r-- | lib/usrp/mboard/usrp2/fw_common.h | 30 |
8 files changed, 213 insertions, 30 deletions
diff --git a/firmware/microblaze/apps/txrx.c b/firmware/microblaze/apps/txrx.c index 5f4c595f8..abea1bf0c 100644 --- a/firmware/microblaze/apps/txrx.c +++ b/firmware/microblaze/apps/txrx.c @@ -156,6 +156,9 @@ void handle_udp_data_packet( _is_data = true; } +#define OTW_GPIO_BANK_TO_NUM(bank) \ + (((bank) == USRP2_GPIO_BANK_RX)? (GPIO_RX_BANK) : (GPIO_TX_BANK)) + void handle_udp_ctrl_packet( struct socket_address src, struct socket_address dst, unsigned char *payload, int payload_len @@ -176,6 +179,9 @@ void handle_udp_ctrl_packet( //handle the data based on the id switch(ctrl_data_in->id){ + /******************************************************************* + * Addressing + ******************************************************************/ case USRP2_CTRL_ID_GIVE_ME_YOUR_IP_ADDR_BRO: ctrl_data_out.id = USRP2_CTRL_ID_THIS_IS_MY_IP_ADDR_DUDE; struct ip_addr ip_addr = get_my_ip_addr(); @@ -194,6 +200,9 @@ void handle_udp_ctrl_packet( ctrl_data_out.data.dboard_ids.rx_id = read_dboard_eeprom(I2C_ADDR_RX_A); break; + /******************************************************************* + * Clock Config + ******************************************************************/ case USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO: //TODO handle MC_PROVIDE_CLK_TO_MIMO when we do MIMO setup ctrl_data_out.id = USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE; @@ -232,6 +241,53 @@ void handle_udp_ctrl_packet( break; + /******************************************************************* + * GPIO + ******************************************************************/ + case USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO: + hal_gpio_set_ddr( + OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.gpio_config.bank), + ctrl_data_in->data.gpio_config.value, + ctrl_data_in->data.gpio_config.mask + ); + ctrl_data_out.id = USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE; + break; + + case USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO: + hal_gpio_write( + OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.gpio_config.bank), + ctrl_data_in->data.gpio_config.value, + ctrl_data_in->data.gpio_config.mask + ); + ctrl_data_out.id = USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE; + break; + + case USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO: + ctrl_data_out.data.gpio_config.value = hal_gpio_read( + OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.gpio_config.bank) + ); + ctrl_data_out.id = USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE; + break; + + case USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO:{ + //setup the atr registers for this bank + int bank = OTW_GPIO_BANK_TO_NUM(ctrl_data_in->data.atr_config.bank); + set_atr_regs( + bank, + ctrl_data_in->data.atr_config.rx_value, + ctrl_data_in->data.atr_config.tx_value + ); + + //setup the sels based on the atr config mask + int mask = ctrl_data_in->data.atr_config.mask; + for (int i = 0; i < 16; i++){ + // set to either GPIO_SEL_SW or GPIO_SEL_ATR + hal_gpio_set_sel(bank, i, (mask & (1 << i)) ? 'a' : 's'); + } + ctrl_data_out.id = USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE; + } + break; + default: ctrl_data_out.id = USRP2_CTRL_ID_HUH_WHAT; diff --git a/firmware/microblaze/lib/db.h b/firmware/microblaze/lib/db.h index 9cd0b379a..5153822c6 100644 --- a/firmware/microblaze/lib/db.h +++ b/firmware/microblaze/lib/db.h @@ -103,4 +103,7 @@ bool db_set_gain(struct db_base *db, u2_fxpt_gain_t gain); +void +set_atr_regs(int bank, int atr_rxval, int atr_txval); + #endif /* INCLUDED_DB_H */ diff --git a/firmware/microblaze/lib/db_init.c b/firmware/microblaze/lib/db_init.c index 4d6081cbc..4a0b49ada 100644 --- a/firmware/microblaze/lib/db_init.c +++ b/firmware/microblaze/lib/db_init.c @@ -105,17 +105,17 @@ lookup_dboard(int i2c_addr, struct db_base *default_db, char *msg) } void -set_atr_regs(int bank, struct db_base *db) +set_atr_regs(int bank, int atr_rxval, int atr_txval) { uint32_t val[4]; int shift; int mask; int i; - val[ATR_IDLE] = 0;//db->atr_rxval; - val[ATR_RX] = 0;//db->atr_rxval; - val[ATR_TX] = 0;//db->atr_txval; - val[ATR_FULL] = 0;//db->atr_txval; + val[ATR_IDLE] = atr_rxval; + val[ATR_RX] = atr_rxval; + val[ATR_TX] = atr_txval; + val[ATR_FULL] = atr_txval; if (bank == GPIO_TX_BANK){ mask = 0xffff0000; @@ -139,7 +139,7 @@ set_gpio_mode(int bank, struct db_base *db) int i; hal_gpio_set_ddr(bank, /*db->output_enables*/0, 0xffff); - set_atr_regs(bank, db); + //set_atr_regs(bank, db); for (i = 0; i < 16; i++){ if (/*db->used_pins*/0 & (1 << i)){ diff --git a/include/uhd/usrp/dboard/interface.hpp b/include/uhd/usrp/dboard/interface.hpp index c18247564..68669b99d 100644 --- a/include/uhd/usrp/dboard/interface.hpp +++ b/include/uhd/usrp/dboard/interface.hpp @@ -82,9 +82,9 @@ public: * The mask controls which pins are controlled by ATR. * * \param bank GPIO_TX_BANK or GPIO_RX_BANK - * \param tx_value 16-bits, 0=FPGA input, 1=FPGA output - * \param rx_value 16-bits, 0=FPGA input, 1=FPGA output - * \param mask 16-bits, 0=ignore, 1=atr + * \param tx_value 16-bits, 0=FPGA output low, 1=FPGA output high + * \param rx_value 16-bits, 0=FPGA output low, 1=FPGA output high + * \param mask 16-bits, 0=software, 1=atr */ virtual void set_atr_reg(gpio_bank_t bank, uint16_t tx_value, uint16_t rx_value, uint16_t mask) = 0; diff --git a/lib/CMakeLists.txt b/lib/CMakeLists.txt index 0e2c6f44d..295943a6f 100644 --- a/lib/CMakeLists.txt +++ b/lib/CMakeLists.txt @@ -35,6 +35,7 @@ ADD_LIBRARY(uhd SHARED usrp/mboard/usrp2.cpp usrp/mboard/usrp2/impl_base.cpp usrp/mboard/usrp2/dboard_impl.cpp + usrp/mboard/usrp2/dboard_interface.cpp ) TARGET_LINK_LIBRARIES(uhd ${Boost_LIBRARIES}) diff --git a/lib/usrp/mboard/usrp2/dboard_interface.cpp b/lib/usrp/mboard/usrp2/dboard_interface.cpp new file mode 100644 index 000000000..05d29daef --- /dev/null +++ b/lib/usrp/mboard/usrp2/dboard_interface.cpp @@ -0,0 +1,111 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include <uhd/utils.hpp> +#include "dboard_interface.hpp" +#include "fw_common.h" + +/*********************************************************************** + * Structors + **********************************************************************/ +dboard_interface::dboard_interface(impl_base *impl){ + _impl = impl; +} + +dboard_interface::~dboard_interface(void){ + /* NOP */ +} + +/*********************************************************************** + * Clock Rates + **********************************************************************/ +double dboard_interface::get_rx_clock_rate(void){ + return _impl->get_master_clock_freq(); +} + +double dboard_interface::get_tx_clock_rate(void){ + return _impl->get_master_clock_freq(); +} + +/*********************************************************************** + * GPIO + **********************************************************************/ +/*! + * Static function to convert a gpio bank enum + * to an over-the-wire value for the usrp2 control. + * \param bank the dboard interface gpio bank enum + * \return an over the wire representation + */ +static uint8_t gpio_bank_to_otw(uhd::usrp::dboard::interface::gpio_bank_t bank){ + switch(bank){ + case uhd::usrp::dboard::interface::GPIO_TX_BANK: return USRP2_GPIO_BANK_TX; + case uhd::usrp::dboard::interface::GPIO_RX_BANK: return USRP2_GPIO_BANK_RX; + } + throw std::runtime_error("unknown gpio bank"); +} + +void dboard_interface::set_gpio_ddr(gpio_bank_t bank, uint16_t value, uint16_t mask){ + //setup the out data + usrp2_ctrl_data_t out_data; + out_data.id = htonl(USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO); + out_data.data.gpio_config.bank = gpio_bank_to_otw(bank); + out_data.data.gpio_config.value = htons(value); + out_data.data.gpio_config.mask = htons(mask); + + //send and recv + usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); + ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE); +} + +void dboard_interface::write_gpio(gpio_bank_t bank, uint16_t value, uint16_t mask){ + //setup the out data + usrp2_ctrl_data_t out_data; + out_data.id = htonl(USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO); + out_data.data.gpio_config.bank = gpio_bank_to_otw(bank); + out_data.data.gpio_config.value = htons(value); + out_data.data.gpio_config.mask = htons(mask); + + //send and recv + usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); + ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE); +} + +uint16_t dboard_interface::read_gpio(gpio_bank_t bank){ + //setup the out data + usrp2_ctrl_data_t out_data; + out_data.id = htonl(USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO); + out_data.data.gpio_config.bank = gpio_bank_to_otw(bank); + + //send and recv + usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); + ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE); + return ntohs(in_data.data.gpio_config.value); +} + +void dboard_interface::set_atr_reg(gpio_bank_t bank, uint16_t tx_value, uint16_t rx_value, uint16_t mask){ + //setup the out data + usrp2_ctrl_data_t out_data; + out_data.id = htonl(USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO); + out_data.data.atr_config.bank = gpio_bank_to_otw(bank); + out_data.data.atr_config.tx_value = htons(tx_value); + out_data.data.atr_config.rx_value = htons(rx_value); + out_data.data.atr_config.mask = htons(mask); + + //send and recv + usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); + ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE); +} diff --git a/lib/usrp/mboard/usrp2/dboard_interface.hpp b/lib/usrp/mboard/usrp2/dboard_interface.hpp index 5afaeb701..645681f43 100644 --- a/lib/usrp/mboard/usrp2/dboard_interface.hpp +++ b/lib/usrp/mboard/usrp2/dboard_interface.hpp @@ -23,25 +23,21 @@ class dboard_interface : public uhd::usrp::dboard::interface{ public: - dboard_interface(impl_base *impl){ - _impl = impl; - } + dboard_interface(impl_base *impl); - ~dboard_interface(void){ - /* NOP */ - } + ~dboard_interface(void); void write_aux_dac(int, int){} int read_aux_adc(int){return 0;} - void set_atr_reg(gpio_bank_t, uint16_t, uint16_t, uint16_t){} + void set_atr_reg(gpio_bank_t, uint16_t, uint16_t, uint16_t); - void set_gpio_ddr(gpio_bank_t, uint16_t, uint16_t){} + void set_gpio_ddr(gpio_bank_t, uint16_t, uint16_t); - void write_gpio(gpio_bank_t, uint16_t, uint16_t){} + void write_gpio(gpio_bank_t, uint16_t, uint16_t); - uint16_t read_gpio(gpio_bank_t){return 0;} + uint16_t read_gpio(gpio_bank_t); void write_i2c (int, const std::string &){} @@ -51,13 +47,9 @@ public: std::string read_spi (spi_dev_t, spi_latch_t, size_t){return "";} - double get_rx_clock_rate(void){ - return _impl->get_master_clock_freq(); - } + double get_rx_clock_rate(void); - double get_tx_clock_rate(void){ - return _impl->get_master_clock_freq(); - } + double get_tx_clock_rate(void); private: impl_base *_impl; diff --git a/lib/usrp/mboard/usrp2/fw_common.h b/lib/usrp/mboard/usrp2/fw_common.h index de4866d8e..8cd15c7c3 100644 --- a/lib/usrp/mboard/usrp2/fw_common.h +++ b/lib/usrp/mboard/usrp2/fw_common.h @@ -51,6 +51,18 @@ typedef enum{ USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO, USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE, + USRP2_CTRL_ID_USE_THESE_GPIO_DDR_SETTINGS_BRO, + USRP2_CTRL_ID_GOT_THE_GPIO_DDR_SETTINGS_DUDE, + + USRP2_CTRL_ID_SET_YOUR_GPIO_PIN_OUTS_BRO, + USRP2_CTRL_ID_I_SET_THE_GPIO_PIN_OUTS_DUDE, + + USRP2_CTRL_ID_GIVE_ME_YOUR_GPIO_PIN_VALS_BRO, + USRP2_CTRL_ID_HERE_IS_YOUR_GPIO_PIN_VALS_DUDE, + + USRP2_CTRL_ID_USE_THESE_ATR_SETTINGS_BRO, + USRP2_CTRL_ID_GOT_THE_ATR_SETTINGS_DUDE, + USRP2_CTRL_ID_PEACE_OUT } usrp2_ctrl_id_t; @@ -71,6 +83,11 @@ typedef enum{ USRP2_REF_SOURCE_MIMO } usrp2_ref_source_t; +typedef enum{ + USRP2_GPIO_BANK_RX, + USRP2_GPIO_BANK_TX +} usrp2_gpio_bank_t; + typedef struct{ uint32_t id; uint32_t seq; @@ -87,16 +104,19 @@ typedef struct{ uint8_t ref_source; uint8_t _pad; } clock_config; - /*struct { + struct { uint8_t bank; - uint16_t ddr; + uint8_t _pad[3]; + uint16_t value; uint16_t mask; - } gpio_ddr_args; + } gpio_config; struct { uint8_t bank; - uint16_t val; + uint8_t _pad[3]; + uint16_t tx_value; + uint16_t rx_value; uint16_t mask; - } gpio_val_args;*/ + } atr_config; } data; } usrp2_ctrl_data_t; |