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| author | Josh Blum <josh@joshknows.com> | 2012-02-04 16:38:54 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-04 16:38:54 -0800 |
| commit | a9d307124faa679df8180b5624e9250555306d67 (patch) | |
| tree | 2bf8fc15ee0e078699ba555729aed882aeb8d266 /usrp2/sdr_lib/dsp_tx_glue.v | |
| parent | 89ce89c9aca6daf7e293b80c70e14a3e2710e137 (diff) | |
| download | uhd-a9d307124faa679df8180b5624e9250555306d67.tar.gz uhd-a9d307124faa679df8180b5624e9250555306d67.tar.bz2 uhd-a9d307124faa679df8180b5624e9250555306d67.zip | |
dsp rework: pass vita clears into dsp modules, unified fifo clears
Diffstat (limited to 'usrp2/sdr_lib/dsp_tx_glue.v')
| -rw-r--r-- | usrp2/sdr_lib/dsp_tx_glue.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/sdr_lib/dsp_tx_glue.v b/usrp2/sdr_lib/dsp_tx_glue.v index 8eccd2bfc..9af13c6c1 100644 --- a/usrp2/sdr_lib/dsp_tx_glue.v +++ b/usrp2/sdr_lib/dsp_tx_glue.v @@ -28,7 +28,7 @@ module dsp_tx_glue ) ( //control signals - input clock, input reset, input enable, + input clock, input reset, input clear, input enable, //user settings bus, controlled through user setting regs API input set_stb, input [7:0] set_addr, input [31:0] set_data, @@ -63,7 +63,7 @@ module dsp_tx_glue `else TX_DSP0_MODULE tx_dsp0_custom ( - .clock(clock), .reset(reset), .enable(enable), + .clock(clock), .reset(reset), .clear(clear), .enable(enable), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .frontend_i(frontend_i), .frontend_q(frontend_q), .duc_out_i(duc_out_i), .duc_out_q(duc_out_q), @@ -81,7 +81,7 @@ module dsp_tx_glue `else TX_DSP1_MODULE tx_dsp1_custom ( - .clock(clock), .reset(reset), .enable(enable), + .clock(clock), .reset(reset), .clear(clear), .enable(enable), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .frontend_i(frontend_i), .frontend_q(frontend_q), .duc_out_i(duc_out_i), .duc_out_q(duc_out_q), |