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| author | Matt Ettus <matt@ettus.com> | 2010-03-26 14:04:22 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-03-26 15:37:50 -0700 |
| commit | 806a2de4cdd9794f6fba915e32534fd2a0f31cb5 (patch) | |
| tree | cecb555cf833917c91db8e3239be0e7e1b675548 /usrp2/opencores/spi/rtl/verilog/timescale.v | |
| parent | 7a3064b67172aea1be00d188bdd79185a7df2ecf (diff) | |
| download | uhd-806a2de4cdd9794f6fba915e32534fd2a0f31cb5.tar.gz uhd-806a2de4cdd9794f6fba915e32534fd2a0f31cb5.tar.bz2 uhd-806a2de4cdd9794f6fba915e32534fd2a0f31cb5.zip | |
remove timescale junk
get rid of asynchronous resets
fix spelling error
corrected comment
Diffstat (limited to 'usrp2/opencores/spi/rtl/verilog/timescale.v')
| -rw-r--r-- | usrp2/opencores/spi/rtl/verilog/timescale.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/usrp2/opencores/spi/rtl/verilog/timescale.v b/usrp2/opencores/spi/rtl/verilog/timescale.v deleted file mode 100644 index 60d4ecbd1..000000000 --- a/usrp2/opencores/spi/rtl/verilog/timescale.v +++ /dev/null @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - |