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| author | Matt Ettus <matt@ettus.com> | 2010-05-10 13:23:48 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-10 13:23:48 -0700 |
| commit | 4a573b5dcc78f9a13162efce09f0bc31f298a818 (patch) | |
| tree | 76529735c6ab6c77943a087285d58ed25d4e4358 /usrp2/opencores/spi/bench/verilog | |
| parent | 45d92a0610582672cea4f1d97d116af00eac7bef (diff) | |
| download | uhd-4a573b5dcc78f9a13162efce09f0bc31f298a818.tar.gz uhd-4a573b5dcc78f9a13162efce09f0bc31f298a818.tar.bz2 uhd-4a573b5dcc78f9a13162efce09f0bc31f298a818.zip | |
proper signal level for 24 bit data
Diffstat (limited to 'usrp2/opencores/spi/bench/verilog')
0 files changed, 0 insertions, 0 deletions