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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
| commit | 8b377a9d6d0ad281474a8dbff49ea3b093178b28 (patch) | |
| tree | 8e3c7a1b60f96df6e2140666d3b7afa5166d885d /usrp2/coregen/coregen.cgp | |
| parent | e92d36dcfe02afaedec348f2d8fc4523fb4e633b (diff) | |
| download | uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.gz uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.bz2 uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.zip | |
moved into subdir
Diffstat (limited to 'usrp2/coregen/coregen.cgp')
| -rw-r--r-- | usrp2/coregen/coregen.cgp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp new file mode 100644 index 000000000..810d64dac --- /dev/null +++ b/usrp2/coregen/coregen.cgp @@ -0,0 +1,20 @@ +# Date: Thu Sep 3 17:40:48 2009 +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +SET workingdirectory = /home/matt/coregen/tmp + |