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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
| commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
| tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /usrp2/control_lib/mux_32_4.v | |
| parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
| download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip | |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'usrp2/control_lib/mux_32_4.v')
| -rw-r--r-- | usrp2/control_lib/mux_32_4.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/usrp2/control_lib/mux_32_4.v b/usrp2/control_lib/mux_32_4.v new file mode 100644 index 000000000..fef5812e9 --- /dev/null +++ b/usrp2/control_lib/mux_32_4.v @@ -0,0 +1,13 @@ + + +module mux_32_4 + (input [1:0] sel, + input [31:0] in0, + input [31:0] in1, + input [31:0] in2, + input [31:0] in3, + output [31:0] out); + + assign out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0); + +endmodule // mux_32_4 |
