Moved usrp1 fpga files into usrp1 subdir.

1 files changed, 16 insertions, 0 deletions

diff --git a/usrp1/sdr_lib/hb/mult.v b/usrp1/sdr_lib/hb/mult.v
new file mode 100644
index 000000000..a8d4cb1b7
--- /dev/null
+++ b/usrp1/sdr_lib/hb/mult.v
@@ -0,0 +1,16 @@
+
+
+module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product,
+	     input enable_in, output reg enable_out );
+
+   always @(posedge clock)
+     if(enable_in)
+       product <= #1 x*y;
+     else
+       product <= #1 31'd0;
+   
+   always @(posedge clock)
+     enable_out <= #1 enable_in;
+   
+endmodule // mult
+