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| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
|---|---|---|
| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /opencores/sd_interface/sim/compile.do | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'opencores/sd_interface/sim/compile.do')
| -rw-r--r-- | opencores/sd_interface/sim/compile.do | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/opencores/sd_interface/sim/compile.do b/opencores/sd_interface/sim/compile.do new file mode 100644 index 000000000..0388e1dbd --- /dev/null +++ b/opencores/sd_interface/sim/compile.do @@ -0,0 +1,22 @@ +
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/dpMem_dc.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/fifoRTL.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/RxFifoBI.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/TxFifoBI.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/RxFifo.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/TxFifo.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/initSD.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSPIWireData.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/readWriteSDBlock.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/sendCmd.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiCtrl.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiTxRxData.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/spiMaster.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../model/wb_master_model.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/wishBoneBI.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../rtl/ctrlStsRegBI.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../model/sdModel.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testHarness.v
+vlog +define+SIM_COMPILE +incdir+../rtl ../bench/testCase0.v
+
+
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