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| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
|---|---|---|
| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /opencores/sd_interface/bench/testHarness.v | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'opencores/sd_interface/bench/testHarness.v')
| -rw-r--r-- | opencores/sd_interface/bench/testHarness.v | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/opencores/sd_interface/bench/testHarness.v b/opencores/sd_interface/bench/testHarness.v new file mode 100644 index 000000000..ce126d67c --- /dev/null +++ b/opencores/sd_interface/bench/testHarness.v @@ -0,0 +1,105 @@ +`include "timescale.v"
+
+module testHarness( );
+
+
+// -----------------------------------
+// Local Wires
+// -----------------------------------
+reg clk;
+reg rst;
+reg spiSysClk;
+wire [7:0] adr;
+wire [7:0] masterDout;
+wire [7:0] masterDin;
+wire stb;
+wire we;
+wire ack;
+wire spiClk;
+wire spiMasterDataIn;
+wire spiMasterDataOut;
+wire spiCS_n;
+
+
+initial begin
+$dumpfile("wave.vcd");
+$dumpvars(0, u_spiMaster);
+end
+
+spiMaster u_spiMaster (
+ //Wishbone bus
+ .clk_i(clk),
+ .rst_i(rst),
+ .address_i(adr),
+ .data_i(masterDout),
+ .data_o(masterDin),
+ .strobe_i(stb),
+ .we_i(we),
+ .ack_o(ack),
+
+ // SPI logic clock
+ .spiSysClk(spiSysClk),
+
+ //SPI bus
+ .spiClkOut(spiClk),
+ .spiDataIn(spiMasterDataIn),
+ .spiDataOut(spiMasterDataOut),
+ .spiCS_n(spiCS_n)
+);
+
+wb_master_model #(.dwidth(8), .awidth(8)) u_wb_master_model (
+ .clk(clk),
+ .rst(rst),
+ .adr(adr),
+ .din(masterDin),
+ .dout(masterDout),
+ .cyc(),
+ .stb(stb),
+ .we(we),
+ .sel(),
+ .ack(ack),
+ .err(1'b0),
+ .rty(1'b0)
+);
+
+sdModel u_sdModel (
+ .spiClk(spiClk),
+ .spiDataIn(spiMasterDataOut),
+ .spiDataOut(spiMasterDataIn),
+ .spiCS_n(spiCS_n)
+);
+//--------------- reset ---------------
+initial begin
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ rst <= 1'b1;
+ @(posedge clk);
+ rst <= 1'b0;
+ @(posedge clk);
+end
+
+// ****************************** Clock section ******************************
+`define CLK_50MHZ_HALF_PERIOD 10
+`define CLK_25MHZ_HALF_PERIOD 20
+
+always begin
+ #`CLK_25MHZ_HALF_PERIOD clk <= 1'b0;
+ #`CLK_25MHZ_HALF_PERIOD clk <= 1'b1;
+end
+
+always begin
+ #`CLK_50MHZ_HALF_PERIOD spiSysClk <= 1'b0;
+ #`CLK_50MHZ_HALF_PERIOD spiSysClk <= 1'b1;
+end
+
+
+
+
+endmodule
+
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