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| author | Dhiren Wijesinghe <dhiren.wijesinghe@ni.com> | 2021-06-18 14:07:18 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-11-03 06:04:50 -0700 |
| commit | c36fc5f6c088efe00eac1f0de32c4377c81fc883 (patch) | |
| tree | bc83ae588edd852d9a5ced2f0a00c4c4fc630140 /mpm/python/x4xx_bist | |
| parent | 426f078ba015f1b0a1521ad447a5a5f79f9fc2a1 (diff) | |
| download | uhd-c36fc5f6c088efe00eac1f0de32c4377c81fc883.tar.gz uhd-c36fc5f6c088efe00eac1f0de32c4377c81fc883.tar.bz2 uhd-c36fc5f6c088efe00eac1f0de32c4377c81fc883.zip | |
mpm: x4xx: add DIO GPIO API configuration methods
These methods allow for reconfiguration of GPIO masters for x4xx.
The method names are get_gpio_banks, get_gpio_srcs, get_gpio_src,
and set_gpio_src.
Diffstat (limited to 'mpm/python/x4xx_bist')
| -rw-r--r-- | mpm/python/x4xx_bist | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/mpm/python/x4xx_bist b/mpm/python/x4xx_bist index 30a9cee48..0c6fb1155 100644 --- a/mpm/python/x4xx_bist +++ b/mpm/python/x4xx_bist @@ -659,8 +659,13 @@ class X4XXBIST(bist.UsrpBIST): mask = 0xDB6D else: mask = 0xFFF - mpm_c.dio_set_pin_masters(inport, mask) - mpm_c.dio_set_pin_masters(outport, mask) + bank_convert = { + "PORTA": "GPIO0", + "PORTB": "GPIO1", + } + ps_control_args = ["MPM"] * 12 + mpm_c.dio_set_gpio_src(bank_convert[inport], ps_control_args) + mpm_c.dio_set_gpio_src(bank_convert[outport], ps_control_args) mpm_c.dio_set_voltage_level(inport, voltage) mpm_c.dio_set_voltage_level(outport, voltage) mpm_c.dio_set_pin_directions(inport, 0x00000) @@ -677,13 +682,13 @@ class X4XXBIST(bist.UsrpBIST): for voltage in ["1V8", "2V5", "3V3"]: for mode in ["DIO", "HDMI"]: for pattern in [0xFFFF, 0xA5A5, 0x5A5A, 0x0000]: - sys.stderr.write("test: PortA -> PortB, {}, {}, 0x{:04X}" + sys.stderr.write("test: PortA -> PortB, {}, {}, 0x{:04X}\n" .format(voltage, mode, pattern)) status, data = _run_sub_test( "PORTB", "PORTA", mode, voltage, pattern) if not status: return status, data - sys.stderr.write("test: PortB -> PortA, {}, {}, 0x{:04X}" + sys.stderr.write("test: PortB -> PortA, {}, {}, 0x{:04X}\n" .format(voltage, mode, pattern)) status, data = _run_sub_test( "PORTA", "PORTB", mode, voltage, pattern) |