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author | Brent Stapleton <brent.stapleton@ettus.com> | 2017-10-30 17:01:44 -0700 |
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committer | Martin Braun <martin.braun@ettus.com> | 2017-12-22 15:04:28 -0800 |
commit | e63a3e8b740e537750e25bc09a82b8b7b557d4d1 (patch) | |
tree | f28a213f199051a1cfea04723724535a1575eb7a /mpm/python/usrp_mpm/periph_manager/n310.py | |
parent | 458655be730602ae3d0b2f4202f6aa334dd38f23 (diff) | |
download | uhd-e63a3e8b740e537750e25bc09a82b8b7b557d4d1.tar.gz uhd-e63a3e8b740e537750e25bc09a82b8b7b557d4d1.tar.bz2 uhd-e63a3e8b740e537750e25bc09a82b8b7b557d4d1.zip |
fpga load: add update_component function to MPM
-update_component takes a byte array containing the data to be written,
and a dictionary containing the metadata of the component to be
updated
-The metadata must contain 'id' and 'filename'
-The metadata may contain an md5 hash ('md5')
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/n310.py')
-rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n310.py | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py index 06d9a444c..50123699a 100644 --- a/mpm/python/usrp_mpm/periph_manager/n310.py +++ b/mpm/python/usrp_mpm/periph_manager/n310.py @@ -624,3 +624,30 @@ class n310(PeriphManagerBase): safe_db_eeprom_user_data[blob_id] = blob.encode('ascii') dboard.set_user_eeprom_data(safe_db_eeprom_user_data) + @no_rpc + def update_fpga(self, filepath, metadata): + """ + Update the FPGA image in the filesystem and reload the overlay + :param filepath: path to new FPGA image + :param metadata: Dictionary of strings containing metadata + """ + self.log.trace("Updating FPGA with image at {}" + .format(filepath)) + _, file_extension = os.path.splitext(filepath) + # Cut off the period from the file extension + file_extension = file_extension[1:].lower() + if file_extension == "bit": + self.log.trace("Converting bit to bin file and writing to {}" + .format(self.binfile_path)) + from usrp_mpm.fpga_bit_to_bin import fpga_bit_to_bin + fpga_bit_to_bin(filepath, self.binfile_path, flip=True) + elif file_extension == "bin": + self.log.trace("Copying bin file to {}" + .format(self.binfile_path)) + shutil.copy(filepath, self.binfile_path) + else: + self.log.error("Invalid FPGA bitfile: {}" + .format(filepath)) + raise RuntimeError("Invalid N310 FPGA bitfile") + # TODO: Implement reload procedure + return True |