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author | Martin Braun <martin.braun@ettus.com> | 2018-03-06 15:45:15 -0800 |
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committer | Martin Braun <martin.braun@ettus.com> | 2018-03-06 15:45:15 -0800 |
commit | f9a8098cae1575a34747af2e212248d3bb189783 (patch) | |
tree | 392697db65e91ad1dc5e9f966eef66e53c7c6d1e /mpm/python/usrp_mpm/dboard_manager/magnesium.py | |
parent | ed2d1ac3e47f107ebef8845130ad60ea2777443c (diff) | |
download | uhd-f9a8098cae1575a34747af2e212248d3bb189783.tar.gz uhd-f9a8098cae1575a34747af2e212248d3bb189783.tar.bz2 uhd-f9a8098cae1575a34747af2e212248d3bb189783.zip |
mpm: Fix some Pylint warnings
No functional changes.
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager/magnesium.py')
-rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/magnesium.py | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py index 7d56dea67..0eaf25ae1 100644 --- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py +++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py @@ -933,8 +933,8 @@ class Magnesium(DboardManagerBase): def dump_jesd_core(self): " Debug method to dump all JESD core regs " with open_uio( - label="dboard-regs-{}".format(self.slot_idx), - read_only=False + label="dboard-regs-{}".format(self.slot_idx), + read_only=False ) as dboard_ctrl_regs: for i in range(0x2000, 0x2110, 0x10): print(("0x%04X " % i), end=' ') @@ -947,8 +947,8 @@ class Magnesium(DboardManagerBase): Debug for accessing the DB Core registers via the RPC shell. """ with open_uio( - label="dboard-regs-{}".format(self.slot_idx), - read_only=False + label="dboard-regs-{}".format(self.slot_idx), + read_only=False ) as dboard_ctrl_regs: rd_data = dboard_ctrl_regs.peek32(addr) self.log.trace("DB Core Register 0x{:04X} response: 0x{:08X}".format(addr, rd_data)) @@ -959,8 +959,8 @@ class Magnesium(DboardManagerBase): Debug for accessing the DB Core registers via the RPC shell. """ with open_uio( - label="dboard-regs-{}".format(self.slot_idx), - read_only=False + label="dboard-regs-{}".format(self.slot_idx), + read_only=False ) as dboard_ctrl_regs: self.log.trace("Writing DB Core Register 0x{:04X} with 0x{:08X}...".format(addr, data)) dboard_ctrl_regs.poke32(addr, data) |