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| author | Martin Braun <martin.braun@ettus.com> | 2015-07-01 13:52:11 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2015-07-14 14:51:32 -0700 |
| commit | 4b1034b29e57a0b405fc89de4602819a4b8cc970 (patch) | |
| tree | abdb2918d100cb2e959165013bffbd461a66b2c4 /host/lib | |
| parent | 7c6bc34f625e3945458a0a2a281850513a02ef08 (diff) | |
| download | uhd-4b1034b29e57a0b405fc89de4602819a4b8cc970.tar.gz uhd-4b1034b29e57a0b405fc89de4602819a4b8cc970.tar.bz2 uhd-4b1034b29e57a0b405fc89de4602819a4b8cc970.zip | |
uhd: Replacing Cheetah w/ Mako 0.4.2 (allows Python 3 compat)
Diffstat (limited to 'host/lib')
22 files changed, 572 insertions, 597 deletions
diff --git a/host/lib/convert/gen_convert_general.py b/host/lib/convert/gen_convert_general.py index b0790755a..8090f14bd 100644 --- a/host/lib/convert/gen_convert_general.py +++ b/host/lib/convert/gen_convert_general.py @@ -17,92 +17,94 @@ # TMPL_HEADER = """ -#import time +<% + import time +%> /*********************************************************************** - * This file was generated by $file on $time.strftime("%c") + * This file was generated by ${file} on ${time.strftime("%c")} **********************************************************************/ -\#include "convert_common.hpp" -\#include <uhd/utils/byteswap.hpp> +#include "convert_common.hpp" +#include <uhd/utils/byteswap.hpp> using namespace uhd::convert; """ TMPL_CONV_GEN2_ITEM32 = """ -DECLARE_CONVERTER(item32, 1, sc16_item32_$(end), 1, PRIORITY_GENERAL){ +DECLARE_CONVERTER(item32, 1, sc16_item32_${end}, 1, PRIORITY_GENERAL){ const item32_t *input = reinterpret_cast<const item32_t *>(inputs[0]); item32_t *output = reinterpret_cast<item32_t *>(outputs[0]); for (size_t i = 0; i < nsamps; i++){ - output[i] = $(to_wire)(input[i]); + output[i] = ${to_wire}(input[i]); } } -DECLARE_CONVERTER(sc16_item32_$(end), 1, item32, 1, PRIORITY_GENERAL){ +DECLARE_CONVERTER(sc16_item32_${end}, 1, item32, 1, PRIORITY_GENERAL){ const item32_t *input = reinterpret_cast<const item32_t *>(inputs[0]); item32_t *output = reinterpret_cast<item32_t *>(outputs[0]); for (size_t i = 0; i < nsamps; i++){ - output[i] = $(to_host)(input[i]); + output[i] = ${to_host}(input[i]); } } """ TMPL_CONV_USRP1_COMPLEX = """ -DECLARE_CONVERTER($(cpu_type), $(width), sc16_item16_usrp1, 1, PRIORITY_GENERAL){ - #for $w in range($width) - const $(cpu_type)_t *input$(w) = reinterpret_cast<const $(cpu_type)_t *>(inputs[$(w)]); - #end for +DECLARE_CONVERTER(${cpu_type}, ${width}, sc16_item16_usrp1, 1, PRIORITY_GENERAL){ + % for w in range(width): + const ${cpu_type}_t *input${w} = reinterpret_cast<const ${cpu_type}_t *>(inputs[${w}]); + % endfor boost::uint16_t *output = reinterpret_cast<boost::uint16_t *>(outputs[0]); for (size_t i = 0, j = 0; i < nsamps; i++){ - #for $w in range($width) - output[j++] = $(to_wire)(boost::uint16_t(boost::int16_t(input$(w)[i].real()$(do_scale)))); - output[j++] = $(to_wire)(boost::uint16_t(boost::int16_t(input$(w)[i].imag()$(do_scale)))); - #end for + % for w in range(width): + output[j++] = ${to_wire}(boost::uint16_t(boost::int16_t(input${w}[i].real()${do_scale}))); + output[j++] = ${to_wire}(boost::uint16_t(boost::int16_t(input${w}[i].imag()${do_scale}))); + % endfor } } -DECLARE_CONVERTER(sc16_item16_usrp1, 1, $(cpu_type), $(width), PRIORITY_GENERAL){ +DECLARE_CONVERTER(sc16_item16_usrp1, 1, ${cpu_type}, ${width}, PRIORITY_GENERAL){ const boost::uint16_t *input = reinterpret_cast<const boost::uint16_t *>(inputs[0]); - #for $w in range($width) - $(cpu_type)_t *output$(w) = reinterpret_cast<$(cpu_type)_t *>(outputs[$(w)]); - #end for + % for w in range(width): + ${cpu_type}_t *output${w} = reinterpret_cast<${cpu_type}_t *>(outputs[${w}]); + % endfor for (size_t i = 0, j = 0; i < nsamps; i++){ - #for $w in range($width) - output$(w)[i] = $(cpu_type)_t( - boost::int16_t($(to_host)(input[j+0]))$(do_scale), - boost::int16_t($(to_host)(input[j+1]))$(do_scale) + % for w in range(width): + output${w}[i] = ${cpu_type}_t( + boost::int16_t(${to_host}(input[j+0]))${do_scale}, + boost::int16_t(${to_host}(input[j+1]))${do_scale} ); j += 2; - #end for + % endfor } } -DECLARE_CONVERTER(sc8_item16_usrp1, 1, $(cpu_type), $(width), PRIORITY_GENERAL){ +DECLARE_CONVERTER(sc8_item16_usrp1, 1, ${cpu_type}, ${width}, PRIORITY_GENERAL){ const boost::uint16_t *input = reinterpret_cast<const boost::uint16_t *>(inputs[0]); - #for $w in range($width) - $(cpu_type)_t *output$(w) = reinterpret_cast<$(cpu_type)_t *>(outputs[$(w)]); - #end for + % for w in range(width): + ${cpu_type}_t *output${w} = reinterpret_cast<${cpu_type}_t *>(outputs[${w}]); + % endfor for (size_t i = 0, j = 0; i < nsamps; i++){ - #for $w in range($width) + % for w in range(width): { - const boost::uint16_t num = $(to_host)(input[j++]); - output$(w)[i] = $(cpu_type)_t( - boost::int8_t(num)$(do_scale), - boost::int8_t(num >> 8)$(do_scale) + const boost::uint16_t num = ${to_host}(input[j++]); + output${w}[i] = ${cpu_type}_t( + boost::int8_t(num)${do_scale}, + boost::int8_t(num >> 8)${do_scale} ); } - #end for + % endfor } } """ def parse_tmpl(_tmpl_text, **kwargs): - from Cheetah.Template import Template - return str(Template(_tmpl_text, kwargs)) + from mako.template import Template + return Template(_tmpl_text).render(**kwargs) if __name__ == '__main__': import sys, os diff --git a/host/lib/ic_reg_maps/common.py b/host/lib/ic_reg_maps/common.py index 24f5bf8be..0351d54a1 100644..100755 --- a/host/lib/ic_reg_maps/common.py +++ b/host/lib/ic_reg_maps/common.py @@ -1,5 +1,5 @@ # -# Copyright 2010-2011 Ettus Research LLC +# Copyright 2010-2011,2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -18,97 +18,91 @@ import re import sys import math -from Cheetah.Template import Template +from mako.template import Template -COMMON_TMPL = """\ -#import time +COMMON_TMPL = """<% import time %>\ /*********************************************************************** - * This file was generated by $file on $time.strftime("%c") + * This file was generated by ${file} on ${time.strftime("%c")} **********************************************************************/ -\#ifndef INCLUDED_$(name.upper())_HPP -\#define INCLUDED_$(name.upper())_HPP +#ifndef INCLUDED_${name.upper()}_HPP +#define INCLUDED_${name.upper()}_HPP -\#include <uhd/config.hpp> -\#include <uhd/exception.hpp> -\#include <boost/cstdint.hpp> -\#include <set> +#include <uhd/config.hpp> +#include <uhd/exception.hpp> +#include <boost/cstdint.hpp> +#include <set> -class $(name)_t{ +class ${name}_t{ public: - #for $reg in $regs - #if $reg.get_enums() - enum $reg.get_type(){ - #for $i, $enum in enumerate($reg.get_enums()) - #set $end_comma = ',' if $i < len($reg.get_enums())-1 else '' - $(reg.get_name().upper())_$(enum[0].upper()) = $enum[1]$end_comma - #end for + % for reg in regs: + % if reg.get_enums(): + enum ${reg.get_type()}{ + % for i,enum in enumerate(reg.get_enums()): + ${reg.get_name().upper()}_${enum[0].upper()} = ${enum[1]}<% comma = ',' if i != (len(reg.get_enums())-1) else '' %>${comma} + % endfor }; - #end if - $reg.get_type() $reg.get_name(); - #end for + % endif + ${reg.get_type()} ${reg.get_name()}; + % endfor - $(name)_t(void){ + ${name}_t(void){ _state = NULL; - #for $reg in $regs - $reg.get_name() = $reg.get_default(); - #end for + % for reg in regs: + ${reg.get_name()} = ${reg.get_default()}; + % endfor } - ~$(name)_t(void){ + ~${name}_t(void){ delete _state; } - $body + ${body} void save_state(void){ - if (_state == NULL) _state = new $(name)_t(); - #for $reg in $regs - _state->$reg.get_name() = this->$reg.get_name(); - #end for + if (_state == NULL) _state = new ${name}_t(); + % for reg in regs: + _state->${reg.get_name()} = this->${reg.get_name()}; + % endfor } template<typename T> std::set<T> get_changed_addrs(void){ if (_state == NULL) throw uhd::runtime_error("no saved state"); //check each register for changes std::set<T> addrs; - #for $reg in $regs - if(_state->$reg.get_name() != this->$reg.get_name()){ - addrs.insert($reg.get_addr()); + % for reg in regs: + if(_state->${reg.get_name()} != this->${reg.get_name()}){ + addrs.insert(${reg.get_addr()}); } - #end for + % endfor return addrs; } - #for $mreg in $mregs - $mreg.get_type() get_$(mreg.get_name())(void){ - return - #set $shift = 0 - #for $reg in $mreg.get_regs() - ($(mreg.get_type())($reg.get_name() & $reg.get_mask()) << $shift) | - #set $shift = $shift + $reg.get_bit_width() - #end for + % for mreg in mregs: + ${mreg.get_type()} get_${mreg.get_name()}(void){ + return <% shift = 0 %> + % for reg in mreg.get_regs(): + (${mreg.get_type()}(${reg.get_name()} & ${reg.get_mask()}) << ${shift}) |<% shift = shift + reg.get_bit_width() %> + % endfor 0; } - void set_$(mreg.get_name())($mreg.get_type() reg){ - #set $shift = 0 - #for $reg in $mreg.get_regs() - $reg.get_name() = (reg >> $shift) & $reg.get_mask(); - #set $shift = $shift + $reg.get_bit_width() - #end for + void set_${mreg.get_name()}(${mreg.get_type()} reg){<% shift = 0 %> + % for reg in mreg.get_regs(): + ${reg.get_name()} = (reg >> ${shift}) & ${reg.get_mask()};<% shift = shift + reg.get_bit_width() %> + % endfor } - #end for + % endfor private: - $(name)_t *_state; + ${name}_t *_state; }; -\#endif /* INCLUDED_$(name.upper())_HPP */ +#endif /* INCLUDED_${name.upper()}_HPP */ """ def parse_tmpl(_tmpl_text, **kwargs): - return str(Template(_tmpl_text, kwargs)) + return Template(_tmpl_text).render(**kwargs) def to_num(arg): return int(eval(arg)) @@ -133,7 +127,8 @@ class reg: self._enums = list() if enums: enum_val = 0 - for enum_str in map(str.strip, enums.split(',')): + for enum_str_unstripped in enums.split(','): + enum_str = enum_str_unstripped.strip() if '=' in enum_str: enum_name, enum_val = enum_str.split('=') enum_val = to_num(enum_val) @@ -146,7 +141,7 @@ class reg: def get_name(self): return self._name def get_default(self): for key, val in self.get_enums(): - if val == self._default: return str.upper('%s_%s'%(self.get_name(), key)) + if val == self._default: return ('%s_%s'%(self.get_name(), key)).upper() return self._default def get_type(self): if self.get_enums(): return '%s_t'%self.get_name() @@ -165,7 +160,7 @@ class mreg: x = re.match('^~(\w*)\s+(.*)\s*$', mreg_des) self._name, reg_names = x.groups() regs_dict = dict([(reg.get_name(), reg) for reg in regs]) - self._regs = [regs_dict[reg_name] for reg_name in map(str.strip, reg_names.split(','))] + self._regs = [regs_dict[reg_name.strip()] for reg_name in reg_names.split(',')] def get_name(self): return self._name def get_regs(self): return self._regs diff --git a/host/lib/ic_reg_maps/gen_ad5623_regs.py b/host/lib/ic_reg_maps/gen_ad5623_regs.py index e653921ba..8b70a9f0a 100755 --- a/host/lib/ic_reg_maps/gen_ad5623_regs.py +++ b/host/lib/ic_reg_maps/gen_ad5623_regs.py @@ -32,9 +32,9 @@ cmd 0[19:21] 0 wr_input_n, up_dac_n, wr_input_n_up_a BODY_TMPL="""\ boost::uint32_t get_reg(void){ boost::uint32_t reg = 0; - #for $reg in filter(lambda r: r.get_addr() == 0, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for reg in filter(lambda r: r.get_addr() == 0, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor return reg; } """ diff --git a/host/lib/ic_reg_maps/gen_ad7922_regs.py b/host/lib/ic_reg_maps/gen_ad7922_regs.py index 5cec1924a..c77991182 100755 --- a/host/lib/ic_reg_maps/gen_ad7922_regs.py +++ b/host/lib/ic_reg_maps/gen_ad7922_regs.py @@ -32,16 +32,16 @@ chn 0[13] 0 BODY_TMPL="""\ boost::uint16_t get_reg(void){ boost::uint16_t reg = 0; - #for $reg in filter(lambda r: r.get_addr() == 0, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for reg in filter(lambda r: r.get_addr() == 0, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor return reg; } void set_reg(boost::uint16_t reg){ - #for $reg in filter(lambda r: r.get_addr() == 0, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for reg in filter(lambda r: r.get_addr() == 0, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor } """ diff --git a/host/lib/ic_reg_maps/gen_ad9510_regs.py b/host/lib/ic_reg_maps/gen_ad9510_regs.py index 6c1e612cc..9f194b5c9 100755 --- a/host/lib/ic_reg_maps/gen_ad9510_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9510_regs.py @@ -54,25 +54,25 @@ lock_detect_disable 0xD[6] 0 enb, dis ######################################################################## ## fine delay adjust ######################################################################## -#for $i, $o in ((5, 0), (6, 4)) -delay_control_out$i $hex(0x34+$o)[0] 0 -ramp_current_out$i $hex(0x35+$o)[0:2] 0 200ua, 400ua, 600ua, 800ua, 1000ua, 1200ua, 1400ua, 1600ua -ramp_capacitor_out$i $hex(0x35+$o)[3:5] 0 4caps=0, 3caps=1, 2caps=3, 1cap=7 -delay_fine_adjust_out$i $hex(0x36+$o)[1:5] 0 -#end for +% for i, o in ((5, 0), (6, 4)): +delay_control_out${i} ${hex(0x34+o)}[0] 0 +ramp_current_out${i} ${hex(0x35+o)}[0:2] 0 200ua, 400ua, 600ua, 800ua, 1000ua, 1200ua, 1400ua, 1600ua +ramp_capacitor_out${i} ${hex(0x35+o)}[3:5] 0 4caps=0, 3caps=1, 2caps=3, 1cap=7 +delay_fine_adjust_out${i} ${hex(0x36+o)}[1:5] 0 +% endfor ######################################################################## ## outputs ######################################################################## -#for $i, $o in ((0, 0), (1, 1), (2, 2), (3, 3)) -power_down_lvpecl_out$i $hex(0x3C+$o)[0:1] 0 normal, test, safe_pd, total_pd -output_level_lvpecl_out$i $hex(0x3C+$o)[2:3] 2 500mv, 340mv, 810mv, 660mv -#end for -#for $i, $o in ((4, 0), (5, 1), (6, 2), (7, 3)) -power_down_lvds_cmos_out$i $hex(0x40+$o)[0] 0 -output_level_lvds_out$i $hex(0x40+$o)[1:2] 1 1_75ma, 3_5ma, 5_25ma, 7ma -lvds_cmos_select_out$i $hex(0x40+$o)[3] 1 lvds, cmos -inverted_cmos_driver_out$i $hex(0x40+$o)[4] 0 dis, enb -#end for +% for i, o in ((0, 0), (1, 1), (2, 2), (3, 3)): +power_down_lvpecl_out${i} ${hex(0x3C+o)}[0:1] 0 normal, test, safe_pd, total_pd +output_level_lvpecl_out${i} ${hex(0x3C+o)}[2:3] 2 500mv, 340mv, 810mv, 660mv +% endfor +% for i, o in ((4, 0), (5, 1), (6, 2), (7, 3)): +power_down_lvds_cmos_out${i} ${hex(0x40+o)}[0] 0 +output_level_lvds_out${i} ${hex(0x40+o)}[1:2] 1 1_75ma, 3_5ma, 5_25ma, 7ma +lvds_cmos_select_out${i} ${hex(0x40+o)}[3] 1 lvds, cmos +inverted_cmos_driver_out${i} ${hex(0x40+o)}[4] 0 dis, enb +% endfor clock_select 0x45[0] 1 clk2_drives, clk1_drives clk1_power_down 0x45[1] 0 clk2_power_down 0x45[2] 0 @@ -82,15 +82,15 @@ all_clock_inputs_pd 0x45[5] 0 ######################################################################## ## dividers ######################################################################## -#for $i, $o in ((0, 0), (1, 2), (2, 4), (3, 6), (4, 8), (5, 10), (6, 12), (7, 14)) -divider_high_cycles_out$i $hex(0x48+$o)[0:3] 0 -divider_low_cycles_out$i $hex(0x48+$o)[4:7] 0 -phase_offset_out$i $hex(0x49+$o)[0:3] 0 -start_out$i $hex(0x49+$o)[4] 0 -force_out$i $hex(0x49+$o)[5] 0 -nosync_out$i $hex(0x49+$o)[6] 0 -bypass_divider_out$i $hex(0x49+$o)[7] 0 -#end for +% for i, o in ((0, 0), (1, 2), (2, 4), (3, 6), (4, 8), (5, 10), (6, 12), (7, 14)): +divider_high_cycles_out${i} ${hex(0x48+o)}[0:3] 0 +divider_low_cycles_out${i} ${hex(0x48+o)}[4:7] 0 +phase_offset_out${i} ${hex(0x49+o)}[0:3] 0 +start_out${i} ${hex(0x49+o)}[4] 0 +force_out${i} ${hex(0x49+o)}[5] 0 +nosync_out${i} ${hex(0x49+o)}[6] 0 +bypass_divider_out${i} ${hex(0x49+o)}[7] 0 +% endfor ######################################################################## ## function ######################################################################## @@ -110,13 +110,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint16_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_ad9522_regs.py b/host/lib/ic_reg_maps/gen_ad9522_regs.py index 1512da811..cc906b76c 100755 --- a/host/lib/ic_reg_maps/gen_ad9522_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9522_regs.py @@ -1,6 +1,6 @@ #!/usr/bin/env python # -# Copyright 2010-2011 Ettus Research LLC +# Copyright 2010-2011,2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -88,39 +88,38 @@ ref2_freq_gt_thresh 0x01F[2] 0 ref1_freq_gt_thresh 0x01F[1] 0 digital_lock_detect 0x01F[0] 0 ######################################################################## -#for $i in range(12) -#set $addr = ($i + 0x0F0) -out$(i)_format $(addr)[7] 0 lvds, cmos -out$(i)_cmos_configuration $(addr)[6:5] 3 off, a_on, b_on, ab_on -out$(i)_polarity $(addr)[4:3] 0 lvds_a_non_b_inv=0, lvds_a_inv_b_non=1, cmos_ab_non=0, cmos_ab_inv=1, cmos_a_non_b_inv=2, cmos_a_inv_b_non=3 -out$(i)_lvds_diff_voltage $(addr)[2:1] 1 1_75ma, 3_5ma, 5_25ma, 7_0ma -out$(i)_lvds_power_down $(addr)[0] 0 -#end for +% for i in range(12): +<% addr = (i + 0x0F0) %>\ +out${i}_format ${addr}[7] 0 lvds, cmos +out${i}_cmos_configuration ${addr}[6:5] 3 off, a_on, b_on, ab_on +out${i}_polarity ${addr}[4:3] 0 lvds_a_non_b_inv=0, lvds_a_inv_b_non=1, cmos_ab_non=0, cmos_ab_inv=1, cmos_a_non_b_inv=2, cmos_a_inv_b_non=3 +out${i}_lvds_diff_voltage ${addr}[2:1] 1 1_75ma, 3_5ma, 5_25ma, 7_0ma +out${i}_lvds_power_down ${addr}[0] 0 +% endfor ######################################################################## -#for $i in reversed(range(8)) -csdld_en_out_$i 0x0FC[$i] 0 ignore, async -#end for +% for i in reversed(range(8)): +csdld_en_out_${i} 0x0FC[${i}] 0 ignore, async +% endfor ######################################################################## -#for $i in reversed(range(4)) -csdld_en_out_$(8 + $i) 0x0FD[$i] 0 ignore, async -#end for +% for i in reversed(range(4)): +csdld_en_out_${8 + i} 0x0FD[${i}] 0 ignore, async +% endfor ######################################################################## -#set $default_val = 0x7 -#for $i in range(4) -#set $addr0 = hex($i*3 + 0x190) -#set $addr1 = hex($i*3 + 0x191) -#set $addr2 = hex($i*3 + 0x192) -divider$(i)_low_cycles $(addr0)[7:4] $default_val -divider$(i)_high_cycles $(addr0)[3:0] $default_val -divider$(i)_bypass $(addr1)[7] 0 -divider$(i)_ignore_sync $(addr1)[6] 0 -divider$(i)_force_high $(addr1)[5] 0 -divider$(i)_start_high $(addr1)[4] 0 -divider$(i)_phase_offset $(addr1)[3:0] 0 -channel$(i)_power_down $(addr2)[2] 0 -disable_divider$(i)_ddc $(addr2)[0] 0 -#set $default_val /= 2 -#end for +% for i in range(4): +<% default_val = int(0x7 / (2**i)) %>\ +<% addr0 = hex(i*3 + 0x190) %>\ +<% addr1 = hex(i*3 + 0x191) %>\ +<% addr2 = hex(i*3 + 0x192) %>\ +divider${i}_low_cycles ${addr0}[7:4] ${default_val} +divider${i}_high_cycles ${addr0}[3:0] ${default_val} +divider${i}_bypass ${addr1}[7] 0 +divider${i}_ignore_sync ${addr1}[6] 0 +divider${i}_force_high ${addr1}[5] 0 +divider${i}_start_high ${addr1}[4] 0 +divider${i}_phase_offset ${addr1}[3:0] 0 +channel${i}_power_down ${addr2}[2] 0 +disable_divider${i}_ddc ${addr2}[0] 0 +% endfor ######################################################################## vco_divider 0x1E0[2:0] 2 div2, div3, div4, div5, div6, static, div1 power_down_clock_input_sel 0x1E1[4] 0 @@ -145,13 +144,13 @@ BODY_TMPL="""\ boost::uint32_t get_reg(boost::uint16_t addr){ boost::uint32_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } if (addr == 0){ //mirror 4 bits in register 0 reg |= ((reg >> 7) & 0x1) << 0; @@ -164,13 +163,13 @@ boost::uint32_t get_reg(boost::uint16_t addr){ void set_reg(boost::uint16_t addr, boost::uint32_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } diff --git a/host/lib/ic_reg_maps/gen_ad9777_regs.py b/host/lib/ic_reg_maps/gen_ad9777_regs.py index 47b61cf44..514283409 100755 --- a/host/lib/ic_reg_maps/gen_ad9777_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9777_regs.py @@ -91,13 +91,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_ad9862_regs.py b/host/lib/ic_reg_maps/gen_ad9862_regs.py index 00340224c..022d97c16 100755 --- a/host/lib/ic_reg_maps/gen_ad9862_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9862_regs.py @@ -41,10 +41,10 @@ all_rx_pd 1[0] 0 ######################################################################## ## Rx A and B ######################################################################## -#for $x, $i in (('a', 2), ('b', 3)) -byp_buffer_$x $(i)[7] 0 -rx_pga_$x $(i)[0:4] 0 -#end for +% for x, i in (('a', 2), ('b', 3)): +byp_buffer_${x} ${i}[7] 0 +rx_pga_${x} ${i}[0:4] 0 +% endfor ######################################################################## ## Rx Misc ######################################################################## @@ -76,13 +76,13 @@ tx_analog_pd 8[0:2] 0 none=0, txb=4, txa=2, both=7 ######################################################################## ## Tx Offset and Gain ######################################################################## -#for $x, $i, $j, $k in (('a', 10, 11, 14), ('b', 12, 13, 15)) -dac_$(x)_offset_1_0 $(i)[6:7] 0 -dac_$(x)_offset_dir $(i)[0] 0 neg_diff, pos_dif -dac_$(x)_offset_9_2 $(j)[0:7] 0 -dac_$(x)_coarse_gain $(k)[6:7] 0 -dac_$(x)_fine_gain $(k)[0:5] 0 -#end for +% for x, i, j, k in (('a', 10, 11, 14), ('b', 12, 13, 15)): +dac_${x}_offset_1_0 ${i}[6:7] 0 +dac_${x}_offset_dir ${i}[0] 0 neg_diff, pos_dif +dac_${x}_offset_9_2 ${j}[0:7] 0 +dac_${x}_coarse_gain ${k}[6:7] 0 +dac_${x}_fine_gain ${k}[0:5] 0 +% endfor tx_pga_gain 16[0:7] 0 ######################################################################## ## Tx Misc @@ -139,20 +139,20 @@ dis1 25[0] 0 enb, dis ######################################################################## ## Aux ADC ######################################################################## -#for $x, $i in (('a2', 26), ('a1', 28), ('b2', 30), ('b1', 32)) -aux_adc_$(x)_1_0 $(i)[6:7] 0 -aux_adc_$(x)_9_2 $int(1+$i)[0:7] 0 -#end for +% for x, i in (('a2', 26), ('a1', 28), ('b2', 30), ('b1', 32)): +aux_adc_${x}_1_0 ${i}[6:7] 0 +aux_adc_${x}_9_2 ${int(1+i)}[0:7] 0 +% endfor ######################################################################## ## Aux ADC Control ######################################################################## aux_spi 34[7] 0 dis, enb sel_bnota 34[6] 0 adc_a, adc_b -#for $x, $i in (('b', 5), ('a', 2)) -refsel_$(x) 34[$i] 0 external, internal -select_$(x) 34[$int($i-1)] 0 aux_adc2, aux_adc1 -start_$(x) 34[$int($i-2)] 0 -#end for +% for x, i in (('b', 5), ('a', 2)): +refsel_${x} 34[${i}] 0 external, internal +select_${x} 34[${int(i-1)}] 0 aux_adc2, aux_adc1 +start_${x} 34[${int(i-2)}] 0 +% endfor ######################################################################## ## Aux ADC Clock ######################################################################## @@ -160,9 +160,9 @@ clk_4 35[0] 0 1_2, 1_4 ######################################################################## ## Aux DAC ######################################################################## -#for $x, $i in (('a', 36), ('b', 37), ('c', 38)) -aux_dac_$x $(i)[0:7] 0 -#end for +% for x, i in (('a', 36), ('b', 37), ('c', 38)): +aux_dac_${x} ${i}[0:7] 0 +% endfor ######################################################################## ## Aux DAC Update ######################################################################## @@ -205,26 +205,26 @@ BODY_TMPL=""" boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in range(0, 63+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint16_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(0, 63+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint16_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } void set_reg(boost::uint8_t addr, boost::uint16_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } diff --git a/host/lib/ic_reg_maps/gen_adf4350_regs.py b/host/lib/ic_reg_maps/gen_adf4350_regs.py index fce2f569b..644654dee 100755 --- a/host/lib/ic_reg_maps/gen_adf4350_regs.py +++ b/host/lib/ic_reg_maps/gen_adf4350_regs.py @@ -43,8 +43,8 @@ power_down 2[5] 0 disabled, enabled pd_polarity 2[6] 1 negative, positive ldp 2[7] 0 10ns, 6ns ldf 2[8] 0 frac_n, int_n -#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(round(x*31.27 + 31.27)/100)).split('.')), range(0,16))) -charge_pump_current 2[9:12] 5 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(round(x*31.27 + 31.27)/100)).split('.')), range(0,16))) %>\ +charge_pump_current 2[9:12] 5 ${current_setting_enums} double_buffer 2[13] 0 disabled, enabled r_counter_10_bit 2[14:23] 0 reference_divide_by_2 2[24] 1 disabled, enabled @@ -101,13 +101,13 @@ enum addr_t{ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint32_t reg = addr & 0x7; switch(addr){ - #for $addr in range(5+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(5+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_adf4351_regs.py b/host/lib/ic_reg_maps/gen_adf4351_regs.py index 4b0ef788c..6699e5137 100755 --- a/host/lib/ic_reg_maps/gen_adf4351_regs.py +++ b/host/lib/ic_reg_maps/gen_adf4351_regs.py @@ -44,8 +44,8 @@ power_down 2[5] 0 disabled, enabled pd_polarity 2[6] 1 negative, positive ldp 2[7] 0 10ns, 6ns ldf 2[8] 0 frac_n, int_n -#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(round(x*31.27 + 31.27)/100)).split('.')), range(0,16))) -charge_pump_current 2[9:12] 5 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(round(x*31.27 + 31.27)/100)).split('.')), range(0,16))) %>\ +charge_pump_current 2[9:12] 5 ${current_setting_enums} double_buffer 2[13] 0 disabled, enabled r_counter_10_bit 2[14:23] 0 reference_divide_by_2 2[24] 1 disabled, enabled @@ -105,13 +105,13 @@ enum addr_t{ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint32_t reg = addr & 0x7; switch(addr){ - #for $addr in range(5+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(5+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_adf4360_regs.py b/host/lib/ic_reg_maps/gen_adf4360_regs.py index 3fd8707a7..921f014ff 100755 --- a/host/lib/ic_reg_maps/gen_adf4360_regs.py +++ b/host/lib/ic_reg_maps/gen_adf4360_regs.py @@ -32,9 +32,9 @@ charge_pump_output 0[9] 0 normal, 3state cp_gain_0 0[10] 0 set1, set2 mute_till_ld 0[11] 0 dis, enb output_power_level 0[12:13] 0 3_5ma, 5_0ma, 7_5ma, 11_0ma -#set $current_setting_enums = ', '.join(map(lambda x: x+"ma", "0_31 0_62 0_93 1_25 1_56 1_87 2_18 2_50".split())) -current_setting1 0[14:16] 0 $current_setting_enums -current_setting2 0[17:19] 0 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: x+"ma", "0_31 0_62 0_93 1_25 1_56 1_87 2_18 2_50".split())) %>\ +current_setting1 0[14:16] 0 ${current_setting_enums} +current_setting2 0[17:19] 0 ${current_setting_enums} power_down 0[20:21] 0 normal_op=0, async_pd=1, sync_pd=3 prescaler_value 0[22:23] 0 8_9, 16_17, 32_33 ######################################################################## @@ -68,13 +68,13 @@ enum addr_t{ boost::uint32_t get_reg(addr_t addr){ boost::uint32_t reg = addr & 0x3; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_ads62p44_regs.py b/host/lib/ic_reg_maps/gen_ads62p44_regs.py index f0a84d940..df5c0c66c 100755 --- a/host/lib/ic_reg_maps/gen_ads62p44_regs.py +++ b/host/lib/ic_reg_maps/gen_ads62p44_regs.py @@ -95,13 +95,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_ads62p48_regs.py b/host/lib/ic_reg_maps/gen_ads62p48_regs.py index c38ce8ff1..fa5668d4f 100644..100755 --- a/host/lib/ic_reg_maps/gen_ads62p48_regs.py +++ b/host/lib/ic_reg_maps/gen_ads62p48_regs.py @@ -55,13 +55,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_lmk04816_regs.py b/host/lib/ic_reg_maps/gen_lmk04816_regs.py index d1f0633a4..d432ac706 100644..100755 --- a/host/lib/ic_reg_maps/gen_lmk04816_regs.py +++ b/host/lib/ic_reg_maps/gen_lmk04816_regs.py @@ -1,4 +1,4 @@ -#Copyright 2010 Ettus Research LLC +#Copyright 2010,2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -94,15 +94,15 @@ CLKout10_11_PD 5[31] 1 normal, power_down ######################################################################## ## address 6 ######################################################################## -#set $CLKoutX_TYPE_ENUMS = "p_down=0, LVDS=1, LVPECL_700mVpp=2, LVPECL_1200mVpp=3, LVPECL_1600mVpp=4, LVPECL_200mVpp=5, LVCMOS=6, LVCMOS_IN=7, LVCMOS_NN=8, LVCMOS_II=9, LVCMOS_LN=10, LVCMOS_LI=11, LVCMOS_NL=12, LVCMOS_IL=13, LVCMOS_LL=1" +<% CLKoutX_TYPE_ENUMS = "p_down=0, LVDS=1, LVPECL_700mVpp=2, LVPECL_1200mVpp=3, LVPECL_1600mVpp=4, LVPECL_200mVpp=5, LVCMOS=6, LVCMOS_IN=7, LVCMOS_NN=8, LVCMOS_II=9, LVCMOS_LN=10, LVCMOS_LI=11, LVCMOS_NL=12, LVCMOS_IL=13, LVCMOS_LL=1" %>\ address6 6[0:4] 6 CLKout0_1_ADLY 6[5:9] 0 Required_6_10 6[10] 0 CLKout2_3_ADLY 6[11:15] 0 -CLKout0_TYPE 6[16:19] 0 $(CLKoutX_TYPE_ENUMS) -CLKout1_TYPE 6[20:23] 0 $(CLKoutX_TYPE_ENUMS) -CLKout2_TYPE 6[24:27] 0 $(CLKoutX_TYPE_ENUMS) -CLKout3_TYPE 6[28:31] 0 $(CLKoutX_TYPE_ENUMS) +CLKout0_TYPE 6[16:19] 0 ${CLKoutX_TYPE_ENUMS} +CLKout1_TYPE 6[20:23] 0 ${CLKoutX_TYPE_ENUMS} +CLKout2_TYPE 6[24:27] 0 ${CLKoutX_TYPE_ENUMS} +CLKout3_TYPE 6[28:31] 0 ${CLKoutX_TYPE_ENUMS} ######################################################################## ## address 7 ######################################################################## @@ -110,21 +110,21 @@ address7 7[0:4] 7 CLKout4_5_ADLY 7[5:9] 0 Required_7_10 7[10] 0 CLKout6_7_ADLY 7[11:15] 0 -CLKout4_TYPE 7[16:19] 0 $(CLKoutX_TYPE_ENUMS) -CLKout5_TYPE 7[20:23] 0 $(CLKoutX_TYPE_ENUMS) -CLKout6_TYPE 7[24:27] 0 $(CLKoutX_TYPE_ENUMS) -CLKout7_TYPE 7[28:31] 0 $(CLKoutX_TYPE_ENUMS) +CLKout4_TYPE 7[16:19] 0 ${CLKoutX_TYPE_ENUMS} +CLKout5_TYPE 7[20:23] 0 ${CLKoutX_TYPE_ENUMS} +CLKout6_TYPE 7[24:27] 0 ${CLKoutX_TYPE_ENUMS} +CLKout7_TYPE 7[28:31] 0 ${CLKoutX_TYPE_ENUMS} ######################################################################## ## address 8 ######################################################################## address8 8[0:4] 8 CLKout8_9_ADLY 8[5:9] 0 Required_8_10 8[10] 0 -CLKout10_11_ADLY 8[11:15] 0 $(CLKoutX_TYPE_ENUMS) -CLKout8_TYPE 8[16:19] 0 $(CLKoutX_TYPE_ENUMS) -CLKout9_TYPE 8[20:23] 0 $(CLKoutX_TYPE_ENUMS) -CLKout10_TYPE 8[24:27] 0 $(CLKoutX_TYPE_ENUMS) -CLKout11_TYPE 8[28:31] 0 $(CLKoutX_TYPE_ENUMS) +CLKout10_11_ADLY 8[11:15] 0 ${CLKoutX_TYPE_ENUMS} +CLKout8_TYPE 8[16:19] 0 ${CLKoutX_TYPE_ENUMS} +CLKout9_TYPE 8[20:23] 0 ${CLKoutX_TYPE_ENUMS} +CLKout10_TYPE 8[24:27] 0 ${CLKoutX_TYPE_ENUMS} +CLKout11_TYPE 8[28:31] 0 ${CLKoutX_TYPE_ENUMS} ######################################################################## ## address 9 ######################################################################## @@ -378,22 +378,18 @@ BODY_TMPL = """\ boost::uint32_t get_reg(int addr){ boost::uint32_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } """ - - - - if __name__ == '__main__': import common; common.generate( name='lmk04816_regs', @@ -402,6 +398,3 @@ if __name__ == '__main__': file=__file__, ) - - - diff --git a/host/lib/ic_reg_maps/gen_max2112_regs.py b/host/lib/ic_reg_maps/gen_max2112_regs.py index c2fc4e3e2..be760ec2e 100755 --- a/host/lib/ic_reg_maps/gen_max2112_regs.py +++ b/host/lib/ic_reg_maps/gen_max2112_regs.py @@ -53,13 +53,14 @@ f_divider_lsb 4[0:7] 0x84 ######################################################################## ## XTAL-Divider R-Divider (5) Write ######################################################################## -#set $xtal_divider_names = ', '.join(map(lambda x: 'div' + str(x), range(1,9))) -xtal_divider 5[5:7] 0 $xtal_divider_names +<% xtal_divider_names = ', '.join(map(lambda x: 'div' + str(x), range(1,9))) %>\ +xtal_divider 5[5:7] 0 ${xtal_divider_names} r_divider 5[0:4] 1 ######################################################################## ## PLL (6) Write ######################################################################## -d24 6[7] 1 div2, div4 ## div2 for LO <= 1125M, div4 > 1125M +## div2 for LO <= 1125M, div4 > 1125M +d24 6[7] 1 div2, div4 cps 6[6] 1 i_cp_from_icp, i_cp_from_vas icp 6[5] 0 i_cp_600ua, i_cp_1200ua ##reserved 6[0:4] 0 @@ -73,7 +74,8 @@ ade 7[0] 1 disabled, enabled ######################################################################## ## LPF (8) Write ######################################################################## -lp 8[0:7] 0x4B ## map(lambda x: "%0.2f"%((4e6 + (x - 12) * 290e3)/1e6), range(255)) in MHz +## map(lambda x: "%0.2f"%((4e6 + (x - 12) * 290e3)/1e6), range(255)) in MHz +lp 8[0:7] 0x4B ######################################################################## ## Control (9) Write ######################################################################## @@ -81,7 +83,8 @@ stby 9[7] 0 normal, disable_sig_and_synth ##reserved 9[6] 0 pwdn 9[5] 0 normal, invalid ##reserved 9[4] 0 -bbg 9[0:3] 0 ## Baseband Gain in dB +## Baseband Gain in dB +bbg 9[0:3] 0 ######################################################################## ## Shutdown (0xA) Write ######################################################################## @@ -118,7 +121,8 @@ ld 0xC[4] 0 unlocked, locked ######################################################################## ## Status Byte-2 (0xD) Read ######################################################################## -vcosbr 0xD[3:7] 0 ## vco band readback +## vco band readback +vcosbr 0xD[3:7] 0 adc 0xD[0:2] 0 ool0, lock0, vaslock0, vaslock1, vaslock2, vaslock3, lock1, ool1 """ @@ -129,41 +133,30 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return boost::uint8_t(reg); } void set_reg(boost::uint8_t addr, boost::uint8_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } """ -SPLIT_REGS_HELPER_TMPL="""\ -#for $divname in ['n','f'] -void set_$(divname)_divider(boost::uint32_t $divname){ - #for $regname in sorted(map(lambda r: r.get_name(), filter(lambda r: r.get_name().find(divname + '_divider') == 0, $regs))) - #end for -} -#end for -""" - #$regname = boost::uint8_t($divname & $regs[regname].get_mask()); - #$divname = boost::uint32_t($divname >> $regs[regname].get_shift()); - if __name__ == '__main__': import common; common.generate( name='max2112_write_regs', diff --git a/host/lib/ic_reg_maps/gen_max2118_regs.py b/host/lib/ic_reg_maps/gen_max2118_regs.py index 506fbaec8..01d7615de 100755 --- a/host/lib/ic_reg_maps/gen_max2118_regs.py +++ b/host/lib/ic_reg_maps/gen_max2118_regs.py @@ -38,28 +38,31 @@ n_divider_lsb 1[0:7] 0xB6 ######################################################################## ## R, Charge Pump, and VCO (2) Write ######################################################################## -#set $r_divider_names = ', '.join(map(lambda x: 'div' + str(2**(x+1)), range(0,8))) -r_divider 2[5:7] 1 $r_divider_names -#set $cp_current_bias = ', '.join(map(lambda x: 'i_cp_%dua'%(50*2**x), range(0,4))) -cp_current 2[3:4] 3 $cp_current_bias +<% r_divider_names = ', '.join(map(lambda x: 'div' + str(2**(x+1)), range(0,8))) %>\ +r_divider 2[5:7] 1 ${r_divider_names} +<% cp_current_bias = ', '.join(map(lambda x: 'i_cp_%dua'%(50*2**x), range(0,4))) %>\ +cp_current 2[3:4] 3 ${cp_current_bias} osc_band 2[0:2] 5 ######################################################################## ## I/Q Filter DAC (3) Write ######################################################################## ##unused 3[7] 0 -f_dac 3[0:6] 0x7F ## filter tuning dac, depends on m +## filter tuning dac, depends on m +f_dac 3[0:6] 0x7F ######################################################################## ## LPF Divider DAC (4) Write ######################################################################## adl_vco_adc_latch 4[7] 0 disabled, enabled ade_vco_ade_read 4[6] 0 disabled, enabled dl_output_drive 4[5] 0 iq_590m_vpp, iq_1_vpp -m_divider 4[0:4] 2 ## filter tuning counter +## filter tuning counter +m_divider 4[0:4] 2 ######################################################################## ## GC2 and Diag (5) Write ######################################################################## diag 5[5:7] 0 normal, cp_i_source, cp_i_sink, cp_high_z, unused, n_and_filt, r_and_gc2, m_div -gc2 5[0:4] 0x1F ## Step Size: 0-1: 0dB, 2-22: 1dB, 23-31: 0.5dB +## Step Size: 0-1: 0dB, 2-22: 1dB, 23-31: 0.5dB +gc2 5[0:4] 0x1F """ ######################################################################## @@ -71,11 +74,13 @@ READ_REGS_TMPL="""\ ## Status (0) Read ######################################################################## pwr 0[6] 0 not_reset, reset -adc 0[2:4] 0 ## VCO tuning voltage, Lock Status +## VCO tuning voltage, Lock Status +adc 0[2:4] 0 ######################################################################## ## I/Q Filter DAC (1) Read ######################################################################## -filter_dac 1[0:6] 0 ## I/Q Filter tuning DAC, current +## I/Q Filter tuning DAC, current +filter_dac 1[0:6] 0 """ ######################################################################## @@ -85,26 +90,26 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return boost::uint8_t(reg); } void set_reg(boost::uint8_t addr, boost::uint8_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } """ diff --git a/host/lib/ic_reg_maps/gen_max2829_regs.py b/host/lib/ic_reg_maps/gen_max2829_regs.py index 383131c18..dbcb68ec9 100755 --- a/host/lib/ic_reg_maps/gen_max2829_regs.py +++ b/host/lib/ic_reg_maps/gen_max2829_regs.py @@ -112,13 +112,13 @@ BODY_TMPL="""\ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint16_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint16_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint16_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return (boost::uint32_t(reg) << 4) | (addr & 0xf); } diff --git a/host/lib/ic_reg_maps/gen_max2870_regs.py b/host/lib/ic_reg_maps/gen_max2870_regs.py index f26c27281..af4e3c786 100644..100755 --- a/host/lib/ic_reg_maps/gen_max2870_regs.py +++ b/host/lib/ic_reg_maps/gen_max2870_regs.py @@ -28,8 +28,10 @@ REGS_TMPL="""\ ## Write-only, default = 0x007D0000 ######################################################################## int_n_mode 0x00[31] 0 frac_n, int_n -int_16_bit 0x00[15:30] 0x007D ##Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode. -frac_12_bit 0x00[3:14] 0 ##Frac divider: 0-4095 +## Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode. +int_16_bit 0x00[15:30] 0x007D +## Frac divider: 0-4095 +frac_12_bit 0x00[3:14] 0 ######################################################################## ## Address 0x01 ## Charge pump control @@ -38,8 +40,10 @@ frac_12_bit 0x00[3:14] 0 ##Frac divider: 0-4095 cpoc 0x01[31] 0 disabled, enabled cpl 0x01[29:30] 1 disabled, enabled, res1, res2 cpt 0x01[27:28] 0 normal, reserved, force_source, force_sink -phase_12_bit 0x01[15:26] 1 ##sets phase shift -mod_12_bit 0x01[3:14] 0xFFF ##VCO frac modulus +## sets phase shift +phase_12_bit 0x01[15:26] 1 +## VCO frac modulus +mod_12_bit 0x01[3:14] 0xFFF ######################################################################## ## Address 0x02 ## Misc. control @@ -50,10 +54,11 @@ low_noise_and_spur 0x02[29:30] 3 low_noise, reserved, low_spur_1, muxout 0x02[26:28] 1 tri_state, high, low, rdiv, ndiv, ald, dld, res7 reference_doubler 0x02[25] 0 disabled, enabled reference_divide_by_2 0x02[24] 0 disabled, enabled -r_counter_10_bit 0x02[14:23] 1 ##R divider value, 1-1023 +## R divider value, 1-1023 +r_counter_10_bit 0x02[14:23] 1 double_buffer 0x02[13] 0 disabled, enabled -#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16))) -charge_pump_current 0x02[9:12] 7 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16))) %>\ +charge_pump_current 0x02[9:12] 7 ${current_setting_enums} ldf 0x02[8] 0 frac_n, int_n ldp 0x02[7] 0 10ns, 6ns pd_polarity 0x02[6] 1 negative, positive @@ -65,18 +70,22 @@ counter_reset 0x02[3] 0 normal, reset ## VCO control ## Write-only, default = 0x0000000B ######################################################################## -vco 0x03[26:31] 0 ##VCO subband selection, used when VAS disabledd -vas 0x03[25] 0 enabled, disabled ##VCO autoselect +## VCO subband selection, used when VAS disabledd +vco 0x03[26:31] 0 +## VCO autoselect +vas 0x03[25] 0 enabled, disabled retune 0x03[24] 1 disabled, enabled clock_div_mode 0x03[15:16] 0 clock_divider_off, fast_lock, phase, reserved -clock_divider_12_bit 0x03[3:14] 1 ##clock divider, 1-4095 +## clock divider, 1-4095 +clock_divider_12_bit 0x03[3:14] 1 ######################################################################## ## Address 0x04 ## RF output control ## Write-only, default = 0x6180B23C ######################################################################## res4 0x04[26:31] 0x18 -bs_msb 0x04[24:25] 0 ##Band select MSBs +## Band select MSBs +bs_msb 0x04[24:25] 0 feedback_select 0x04[23] 1 divided, fundamental rf_divider_select 0x04[20:22] 0 div1, div2, div4, div8, div16, div32, div64, div128 band_select_clock_div 0x04[12:19] 0 @@ -111,13 +120,13 @@ enum addr_t{ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint32_t reg = addr & 0x7; switch(addr){ - #for $addr in range(5+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(5+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_max2871_regs.py b/host/lib/ic_reg_maps/gen_max2871_regs.py index 338a019d8..f591c1636 100644..100755 --- a/host/lib/ic_reg_maps/gen_max2871_regs.py +++ b/host/lib/ic_reg_maps/gen_max2871_regs.py @@ -28,8 +28,10 @@ REGS_TMPL="""\ ## Write-only, default = 0x007D0000 ######################################################################## int_n_mode 0x00[31] 0 frac_n, int_n -int_16_bit 0x00[15:30] 0x007D ##Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode. -frac_12_bit 0x00[3:14] 0 ##Frac divider: 0-4095 +## Integer divider: 16-65535 in int-N mode, 19-4091 in frac-N mode. +int_16_bit 0x00[15:30] 0x007D +## Frac divider: 0-4095 +frac_12_bit 0x00[3:14] 0 ######################################################################## ## Address 0x01 ## Charge pump control @@ -38,8 +40,10 @@ frac_12_bit 0x00[3:14] 0 ##Frac divider: 0-4095 res1 0x01[31] 0 cpl 0x01[29:30] 1 disabled, enabled, res1, res2 cpt 0x01[27:28] 0 normal, reserved, force_source, force_sink -phase_12_bit 0x01[15:26] 1 ##sets phase shift -mod_12_bit 0x01[3:14] 0xFFF ##VCO frac modulus +## sets phase shift +phase_12_bit 0x01[15:26] 1 +## VCO frac modulus +mod_12_bit 0x01[3:14] 0xFFF ######################################################################## ## Address 0x02 ## Misc. control @@ -50,10 +54,11 @@ low_noise_and_spur 0x02[29:30] 3 low_noise, reserved, low_spur_1, muxout 0x02[26:28] 0x6 tri_state, high, low, rdiv, ndiv, ald, dld, sync, res8, res9, res10, res11, spi, res13, res14, res15 reference_doubler 0x02[25] 0 disabled, enabled reference_divide_by_2 0x02[24] 0 disabled, enabled -r_counter_10_bit 0x02[14:23] 1 ##R divider value, 1-1023 +## R divider value, 1-1023 +r_counter_10_bit 0x02[14:23] 1 double_buffer 0x02[13] 0 disabled, enabled -#set $current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16))) -charge_pump_current 0x02[9:12] 7 $current_setting_enums +<% current_setting_enums = ', '.join(map(lambda x: '_'.join(("%0.2fma"%(1.631/5.1 * (1.+x))).split('.')), range(0,16))) %>\ +charge_pump_current 0x02[9:12] 7 ${current_setting_enums} ldf 0x02[8] 0 frac_n, int_n ldp 0x02[7] 0 10ns, 6ns pd_polarity 0x02[6] 1 negative, positive @@ -65,14 +70,17 @@ counter_reset 0x02[3] 0 normal, reset ## VCO control ## Write-only, default = 0x0000000B ######################################################################## -vco 0x03[26:31] 0 ##VCO subband selection, used when VAS disabledd -shutdown_vas 0x03[25] 0 enabled, disabled ##VCO autoselect +## VCO subband selection, used when VAS disabledd +vco 0x03[26:31] 0 +## VCO autoselect +shutdown_vas 0x03[25] 0 enabled, disabled retune 0x03[24] 1 disabled, enabled res3 0x3[19:23] 0 csm 0x3[18] 0 disabled, enabled mutedel 0x3[17] 0 disabled, enabled clock_div_mode 0x03[15:16] 0 clock_divider_off, fast_lock, phase, reserved -clock_divider_12_bit 0x03[3:14] 1 ##clock divider, 1-4095 +## clock divider, 1-4095 +clock_divider_12_bit 0x03[3:14] 1 ######################################################################## ## Address 0x04 ## RF output control @@ -82,7 +90,8 @@ res4 0x04[29:31] 0x3 shutdown_ldo 0x04[28] 0 enabled, disabled shutdown_div 0x04[27] 0 enabled, disabled shutdown_ref 0x04[26] 0 enabled, disabled -bs_msb 0x04[24:25] 0 ##Band select MSBs +## Band select MSBs +bs_msb 0x04[24:25] 0 feedback_select 0x04[23] 1 divided, fundamental rf_divider_select 0x04[20:22] 0 div1, div2, div4, div8, div16, div32, div64, div128 band_select_clock_div 0x04[12:19] 0 @@ -124,13 +133,13 @@ enum addr_t{ boost::uint32_t get_reg(boost::uint8_t addr){ boost::uint32_t reg = addr & 0x7; switch(addr){ - #for $addr in range(5+1) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint32_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in range(5+1): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint32_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return reg; } diff --git a/host/lib/ic_reg_maps/gen_tda18272hnm_regs.py b/host/lib/ic_reg_maps/gen_tda18272hnm_regs.py index 677a201de..308d7d524 100755 --- a/host/lib/ic_reg_maps/gen_tda18272hnm_regs.py +++ b/host/lib/ic_reg_maps/gen_tda18272hnm_regs.py @@ -28,7 +28,7 @@ REGS_TMPL="""\ ######################################################################## ## ID_byte_1 (0x00) Read ######################################################################## -##reserved as 1 0x00[7] 1 +## reserved as 1 0x00[7] 1 ident_14_8 0x00[0:6] 0 ######################################################################## ## ID_byte_2 (0x01) Read @@ -43,23 +43,25 @@ minor_rev 0x02[0:3] 0 ######################################################################## ## Thermo_byte_1 (0x03) Read ######################################################################## -##reserved 0x03[7] 0 -tm_d 0x03[0:6] 0 ## 22-127deg C junction temp +## reserved 0x03[7] 0 +## 22-127deg C junction temp +tm_d 0x03[0:6] 0 ######################################################################## ## Thermo_byte_2 (0x04) Write ######################################################################## -##reserved 0x04[1:7] 0 +## reserved 0x04[1:7] 0 tm_on 0x04[0] 0 sensor_off, sensor_on ######################################################################## ## Power_state_byte_1 (0x05) Read ######################################################################## -##reserved 0x05[2:7] 0 +## reserved 0x05[2:7] 0 por 0x05[1] 0 read, reset lo_lock 0x05[0] 0 unlocked, locked ######################################################################## -## Power_state_byte_2 (0x06) Read/Write ## Standby modes +## Standby modes +## Power_state_byte_2 (0x06) Read/Write ######################################################################## -##reserved 0x06[4:7] 0 +## reserved 0x06[4:7] 0 sm 0x06[3] 0 normal, standby sm_pll 0x06[2] 0 on, off sm_lna 0x06[1] 0 on, off @@ -68,14 +70,15 @@ sm_lna 0x06[1] 0 on, off ######################################################################## ## Input_Power_Level_byte (0x07) Read ######################################################################## -##reserved 0x07[7] 0 -power_level 0x07[0:6] 0 ## 40dB_Vrms to 110dB_Vrms +## reserved 0x07[7] 0 +## 40dB_Vrms to 110dB_Vrms +power_level 0x07[0:6] 0 ## Trigger power level calculation with MSM_byte_1 and MSM_byte_2 ######################################################################## ## IRQ_status (0x08) Read/Write ######################################################################## irq_status 0x08[7] 0 cleared, set -##reserved 0x08[6] 0 +## reserved 0x08[6] 0 irq_xtalcal_end 0x08[5] 0 false, true irq_rssi_end 0x08[4] 0 false, true irq_localc_end 0x08[3] 0 false, true @@ -86,7 +89,7 @@ irq_rccal_end 0x08[0] 0 false, true ## IRQ_enable (0x09) Read/Write ######################################################################## irq_enable 0x09[7] 1 false, true -##reserved 0x09[6] 0 +## reserved 0x09[6] 0 irq_xtalcal_enable 0x09[5] 0 false, true irq_rssi_enable 0x09[4] 0 false, true irq_localc_enable 0x09[3] 0 false, true @@ -97,7 +100,7 @@ irq_rccal_enable 0x09[0] 0 false, true ## IRQ_clear (0x0a) Read/Write ######################################################################## irq_clear 0x0a[7] 0 false, true -##reserved 0x0a[6] 0 +## reserved 0x0a[6] 0 irq_xtalcal_clear 0x0a[5] 0 false, true irq_rssi_clear 0x0a[4] 0 false, true irq_localc_clear 0x0a[3] 0 false, true @@ -108,7 +111,7 @@ irq_rccal_clear 0x0a[0] 0 false, true ## IRQ_set (0x0b) Read ######################################################################## irq_set 0x0b[7] 0 false, true -##reserved 0x0b[6] 0 +## reserved 0x0b[6] 0 irq_xtalcal_set 0x0b[5] 0 false, true irq_rssi_set 0x0b[4] 0 false, true irq_localc_set 0x0b[3] 0 false, true @@ -120,12 +123,12 @@ irq_rccal_set 0x0b[0] 0 false, true ######################################################################## lt_enable 0x0c[7] 0 agc1_6_15db 0x0c[6] 1 -##reserved 0x0c[4:5] 0 +## reserved 0x0c[4:5] 0 agc1_top 0x0c[0:3] 0 ######################################################################## ## AGC2_byte_1 (0x0d) Read ######################################################################## -##reserved 0x0d[5:7] 0 +## reserved 0x0d[5:7] 0 agc2_top 0x0d[0:4] 0xf ######################################################################## ## AGCK_byte_1 (0x0e) Read/Write @@ -141,24 +144,25 @@ agck_mode 0x0e[0:1] 1 analog_tv=1, digital_tv=2 pd_rfagc_adapt 0x0f[7] 0 on, off rfagc_adapt_top 0x0f[5:6] 0 rfagc_low_bw 0x0f[4] 1 -rf_atten_3db 0x0f[3] 0 0db, 3db ## FIXME +## FIXME +rf_atten_3db 0x0f[3] 0 0db, 3db agc3_top 0x0f[0:2] 1 ######################################################################## ## IR_MIXER_byte_1 (0x10) Read/Write ######################################################################## -##reserved 0x10[4:7] 0 +## reserved 0x10[4:7] 0 agc4_top 0x10[0:3] 1 ######################################################################## ## AGC5_byte_1 (0x11) Read/Write ######################################################################## -##reserved 0x11[7] 0 +## reserved 0x11[7] 0 agcs_do_step_assym 0x11[5:6] 2 agc5_hpf 0x11[4] 1 off, on agc5_top 0x11[0:3] 1 ######################################################################## ## IF_AGC_byte (0x12) Read/Write ######################################################################## -##reserved 0x12[3:7] 0 +## reserved 0x12[3:7] 0 if_level 0x12[0:2] 0 0_5vpp=7, 0_6vpp=6, 0_7vpp=5, 0_85vpp=4, 0_8vpp=3, 1_0vpp=2, 1_25vpp=1, 2_0vpp=0 ######################################################################## ## IF_byte_1 (0x13) Read/Write @@ -172,18 +176,19 @@ lp_fc 0x13[0:2] 3 1_7mhz=4, 6_0mhz=0, 7_0mhz=1, 8_0mhz=2, ######################################################################## i2c_clock_mode 0x14[7] 0 digital_clock 0x14[6] 1 spread_off, spread_on -##reserved 0x14[5] 0 +## reserved 0x14[5] 0 xtalosc_anareg_en 0x14[4] 0 -##reserved 0x14[2:3] 0 +## reserved 0x14[2:3] 0 xtout 0x14[0:1] 0 no=0, 16mhz=3 ######################################################################## ## IF_Frequency_byte (0x15) Read/Write ######################################################################## -if_freq 0x15[0:7] 0 ## IF frequency = if_freq*50 (kHz) +## IF frequency = if_freq*50 (kHz) +if_freq 0x15[0:7] 0 ######################################################################## ## RF_Frequency_byte_1 (0x16) Read/Write ######################################################################## -##reserved 0x16[4:7] 0 +## reserved 0x16[4:7] 0 rf_freq_19_16 0x16[0:3] 0 ######################################################################## ## RF_Frequency_byte_2 (0x17) Read/Write @@ -209,7 +214,7 @@ calc_pll 0x19[0] 0 ######################################################################## ## MSM_byte_2 (0x1a) Read ######################################################################## -##reserved 0x1a[2:7] 0 +## reserved 0x1a[2:7] 0 xtalcal_launch 0x1a[1] 0 msm_launch 0x1a[0] 0 ######################################################################## @@ -227,11 +232,11 @@ psm_lodriver 0x1b[0:1] 0 dcc_bypass 0x1c[7] 0 dcc_slow 0x1c[6] 0 dcc_psm 0x1c[5] 0 -##reserved 0x1c[0:4] 0 +## reserved 0x1c[0:4] 0 ######################################################################## ## FLO_Max_byte (0x1d) Read ######################################################################## -##reserved 0x1d[6:7] 0 +## reserved 0x1d[6:7] 0 fmax_lo 0x1d[0:5] 0xA ######################################################################## ## IR_Cal_byte_1 (0x1e) Read @@ -249,12 +254,12 @@ ir_freqlow 0x1f[0:4] 0 ######################################################################## ## IR_Cal_byte_3 (0x20) Read ######################################################################## -##reserved 0x20[5:7] 0 +## reserved 0x20[5:7] 0 ir_freqmid 0x20[0:4] 0 ######################################################################## ## IR_Cal_byte_4 (0x21) Read ######################################################################## -##reserved 0x21[5:7] 0 +## reserved 0x21[5:7] 0 coarse_ir_freqhigh 0x21[4] 0 ir_freqhigh 0x21[0:3] 0 ######################################################################## @@ -270,8 +275,9 @@ agc_ovld_timer 0x22[0:1] 0 ######################################################################## ir_mixer_loop_off 0x23[7] 0 ir_mixer_do_step 0x23[5:6] 0 -##reserved 0x23[2:4] 0 -hi_pass 0x23[1] 0 disable, enable ## FIXME Logic Unclear +## reserved 0x23[2:4] 0 +## FIXME Logic Unclear +hi_pass 0x23[1] 0 disable, enable if_notch 0x23[0] 1 on, off ######################################################################## ## AGC1_byte_2 (0x24) Read @@ -285,9 +291,9 @@ agc1_gain 0x24[0:3] 8 ######################################################################## agc5_loop_off 0x25[7] 0 agc5_do_step 0x25[5:6] 0 -##reserved 0x25[4] 0 +## reserved 0x25[4] 0 force_agc5_gain 0x25[3] 0 -##reserved 0x25[2] 0 +## reserved 0x25[2] 0 agc5_gain 0x25[0:1] 2 ######################################################################## ## RF_Cal_byte_1 (0x26) Read @@ -335,7 +341,7 @@ rfcal_freq11 0x2b[0:1] 0 ## RF_Filter_byte_1 (0x2c) Read ######################################################################## rf_filter_bypass 0x2c[7] 0 -##reserved as 0 0x2c[6] 0 +## reserved as 0 0x2c[6] 0 agc2_loop_off 0x2c[5] 0 force_agc2_gain 0x2c[4] 0 rf_filter_gv 0x2c[2:3] 2 @@ -353,12 +359,12 @@ gain_taper 0x2e[0:5] 0 ## RF_Band_Pass_Filter_byte (0x2f) Read ######################################################################## rf_bpf_bypass 0x2f[7] 0 -##reserved 0x2f[3:6] 0 +## reserved 0x2f[3:6] 0 rf_bpf 0x2f[0:2] 0 ######################################################################## ## CP_Current_byte (0x30) Read ######################################################################## -##reserved 0x30[7] 0 +## reserved 0x30[7] 0 n_cp_current 0x30[0:6] 0x68 ######################################################################## ## AGC_Det_Out_byte (0x31) Read @@ -374,24 +380,26 @@ do_agc1 0x31[0] 0 ######################################################################## ## RF_AGC_Gain_byte_1 (0x32) Read ######################################################################## -#set $lna_gain_names = ', '.join(map(lambda x: {0: '', 1: 'm'}[3*x-12 < 0] + str(abs(3*x-12)) + 'db=' + str(x), range(0,10))) -##reserved 0x32[6:7] 0 +## reserved 0x32[6:7] 0 agc2_gain_read 0x32[4:5] 3 m11db, m8db, m5db, m2db -agc1_gain_read 0x32[0:3] 9 $lna_gain_names +<% lna_gain_names = ', '.join(map(lambda x: {0: '', 1: 'm'}[3*x-12 < 0] + str(abs(3*x-12)) + 'db=' + str(x), range(0,10))) %>\ +agc1_gain_read 0x32[0:3] 9 ${lna_gain_names} ######################################################################## ## RF_AGC_Gain_byte_2 (0x33) Read ######################################################################## -#set $top_agc3_read_names = ', '.join(map(lambda x: str(int(round(1.92*x+94))) + 'dbuvrms=' + str(x), range(0,8))) -##reserved 0x33[3:7] 0 -top_agc3_read 0x33[0:2] 0 $top_agc3_read_names +## reserved 0x33[3:7] 0 +<% top_agc3_read_names = ', '.join(map(lambda x: str(int(round(1.92*x+94))) + 'dbuvrms=' + str(x), range(0,8))) %>\ +top_agc3_read 0x33[0:2] 0 ${top_agc3_read_names} ######################################################################## ## IF_AGC_Gain_byte (0x34) Read ######################################################################## -#set $lpf_gain_names = ', '.join(map(lambda x: str(3*x) + 'db=' + str(x), range(0,4))) -#set $ir_mixer_names = ', '.join(map(lambda x: str(3*x+2) + 'db=' + str(x), range(0,5))) -##reserved 0x34[5:7] 0 -agc5_gain_read 0x34[3:4] 3 $lpf_gain_names -agc4_gain_read 0x34[0:2] 4 $ir_mixer_names +## reserved 0x34[5:7] 0 +<% + lpf_gain_names = ', '.join(map(lambda x: str(3*x) + 'db=' + str(x), range(0,4))) + ir_mixer_names = ', '.join(map(lambda x: str(3*x+2) + 'db=' + str(x), range(0,5))) +%>\ +agc5_gain_read 0x34[3:4] 3 ${lpf_gain_names} +agc4_gain_read 0x34[0:2] 4 ${ir_mixer_names} ######################################################################## ## Power_byte_1 (0x35) Read ######################################################################## @@ -399,9 +407,9 @@ rssi 0x35[0:7] 0 ######################################################################## ## Power_byte_2 (0x36) Read ######################################################################## -##reserved 0x36[6:7] 0 +## reserved 0x36[6:7] 0 rssi_av 0x36[5] 0 -##reserved 0x36[4] 0 +## reserved 0x36[4] 0 rssi_cap_reset_en 0x36[3] 1 rssi_cap_val 0x36[2] 1 rssi_ck_speed 0x36[1] 0 @@ -479,39 +487,30 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return boost::uint8_t(reg); } void set_reg(boost::uint8_t addr, boost::uint8_t reg){ switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask()); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + ${reg.get_name()} = ${reg.get_type()}((reg >> ${reg.get_shift()}) & ${reg.get_mask()}); + % endfor break; - #end for + % endfor } } """ -SPLIT_REGS_HELPER_TMPL="""\ -#for $divname in ['n','f'] -void set_$(divname)_divider(boost::uint32_t $divname){ - #for $regname in sorted(map(lambda r: r.get_name(), filter(lambda r: r.get_name().find(divname + '_divider') == 0, $regs))) - #end for -} -#end for -""" - if __name__ == '__main__': import common; common.generate( name='tda18272hnm_regs', diff --git a/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py b/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py index 73f7aa3db..9b8e1958f 100644..100755 --- a/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py +++ b/host/lib/ic_reg_maps/gen_tuner_4937di5_regs.py @@ -53,13 +53,13 @@ BODY_TMPL="""\ boost::uint8_t get_reg(boost::uint8_t addr){ boost::uint8_t reg = 0; switch(addr){ - #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) - case $addr: - #for $reg in filter(lambda r: r.get_addr() == addr, $regs) - reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift(); - #end for + % for addr in sorted(set(map(lambda r: r.get_addr(), regs))): + case ${addr}: + % for reg in filter(lambda r: r.get_addr() == addr, regs): + reg |= (boost::uint8_t(${reg.get_name()}) & ${reg.get_mask()}) << ${reg.get_shift()}; + % endfor break; - #end for + % endfor } return boost::uint8_t(reg); } diff --git a/host/lib/transport/gen_vrt_if_packet.py b/host/lib/transport/gen_vrt_if_packet.py index 98f6804ae..6723e3a4b 100644 --- a/host/lib/transport/gen_vrt_if_packet.py +++ b/host/lib/transport/gen_vrt_if_packet.py @@ -1,6 +1,6 @@ #!/usr/bin/env python # -# Copyright 2010-2013 Ettus Research LLC +# Copyright 2010-2013,2015 Ettus Research LLC # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -25,26 +25,25 @@ metatdata into vrt headers and vrt headers into metadata. The generated code infers jump tables to speed-up the parsing time. """ -TMPL_TEXT = """ -#import time +TMPL_TEXT = """<% import time %> /*********************************************************************** - * This file was generated by $file on $time.strftime("%c") + * This file was generated by ${file} on ${time.strftime("%c")} **********************************************************************/ -\#include <uhd/exception.hpp> -\#include <uhd/transport/vrt_if_packet.hpp> -\#include <uhd/utils/byteswap.hpp> -\#include <boost/detail/endian.hpp> -\#include <vector> +#include <uhd/exception.hpp> +#include <uhd/transport/vrt_if_packet.hpp> +#include <uhd/utils/byteswap.hpp> +#include <boost/detail/endian.hpp> +#include <vector> //define the endian macros to convert integers -\#ifdef BOOST_BIG_ENDIAN - \#define BE_MACRO(x) (x) - \#define LE_MACRO(x) uhd::byteswap(x) -\#else - \#define BE_MACRO(x) uhd::byteswap(x) - \#define LE_MACRO(x) (x) -\#endif +#ifdef BOOST_BIG_ENDIAN + #define BE_MACRO(x) (x) + #define LE_MACRO(x) uhd::byteswap(x) +#else + #define BE_MACRO(x) uhd::byteswap(x) + #define LE_MACRO(x) (x) +#endif using namespace uhd; using namespace uhd::transport; @@ -59,13 +58,13 @@ static pred_table_type get_pred_unpack_table(void) pred_table_type table(1 << 9, 0); //only 9 bits useful here (20-28) for (size_t i = 0; i < table.size(); i++){ boost::uint32_t vrt_hdr_word = i << 20; - if(vrt_hdr_word & $hex(0x1 << 28)) table[i] |= $hex($sid_p); - if(vrt_hdr_word & $hex(0x1 << 27)) table[i] |= $hex($cid_p); - if(vrt_hdr_word & $hex(0x3 << 22)) table[i] |= $hex($tsi_p); - if(vrt_hdr_word & $hex(0x3 << 20)) table[i] |= $hex($tsf_p); - if(vrt_hdr_word & $hex(0x1 << 26)) table[i] |= $hex($tlr_p); - if(vrt_hdr_word & $hex(0x1 << 24)) table[i] |= $hex($eob_p); - if(vrt_hdr_word & $hex(0x1 << 25)) table[i] |= $hex($sob_p); + if(vrt_hdr_word & ${hex(0x1 << 28)}) table[i] |= ${hex(sid_p)}; + if(vrt_hdr_word & ${hex(0x1 << 27)}) table[i] |= ${hex(cid_p)}; + if(vrt_hdr_word & ${hex(0x3 << 22)}) table[i] |= ${hex(tsi_p)}; + if(vrt_hdr_word & ${hex(0x3 << 20)}) table[i] |= ${hex(tsf_p)}; + if(vrt_hdr_word & ${hex(0x1 << 26)}) table[i] |= ${hex(tlr_p)}; + if(vrt_hdr_word & ${hex(0x1 << 24)}) table[i] |= ${hex(eob_p)}; + if(vrt_hdr_word & ${hex(0x1 << 25)}) table[i] |= ${hex(sob_p)}; } return table; } @@ -105,13 +104,12 @@ UHD_INLINE static boost::uint32_t vrt_to_chdr(const boost::uint32_t vrt, const i } ######################################################################## -#def gen_code($XE_MACRO, $suffix) +<%def name="gen_code(XE_MACRO, suffix)"> ######################################################################## - /*********************************************************************** - * interal impl of packing VRT IF header only + * internal impl of packing VRT IF header only **********************************************************************/ -UHD_INLINE void __if_hdr_pack_$(suffix)( +UHD_INLINE void __if_hdr_pack_${suffix}( boost::uint32_t *packet_buff, if_packet_info_t &if_packet_info, boost::uint32_t &vrt_hdr_word32 @@ -119,72 +117,53 @@ UHD_INLINE void __if_hdr_pack_$(suffix)( boost::uint32_t vrt_hdr_flags = 0; pred_type pred = 0; - if (if_packet_info.has_sid) pred |= $hex($sid_p); - if (if_packet_info.has_cid) pred |= $hex($cid_p); - if (if_packet_info.has_tsi) pred |= $hex($tsi_p); - if (if_packet_info.has_tsf) pred |= $hex($tsf_p); - if (if_packet_info.has_tlr) pred |= $hex($tlr_p); - if (if_packet_info.eob) pred |= $hex($eob_p); - if (if_packet_info.sob) pred |= $hex($sob_p); + if (if_packet_info.has_sid) pred |= ${hex(sid_p)}; + if (if_packet_info.has_cid) pred |= ${hex(cid_p)}; + if (if_packet_info.has_tsi) pred |= ${hex(tsi_p)}; + if (if_packet_info.has_tsf) pred |= ${hex(tsf_p)}; + if (if_packet_info.has_tlr) pred |= ${hex(tlr_p)}; + if (if_packet_info.eob) pred |= ${hex(eob_p)}; + if (if_packet_info.sob) pred |= ${hex(sob_p)}; switch(pred){ - #for $pred in range(2**7) - case $pred: - #set $num_header_words = 1 - #set $flags = 0 + % for pred in range(2**7): + case ${pred}:<% num_header_words = 1 %><% flags = 0 %> ########## Stream ID ########## - #if $pred & $sid_p - packet_buff[$num_header_words] = $(XE_MACRO)(if_packet_info.sid); - #set $num_header_words += 1 - #set $flags |= (0x1 << 28); - #end if + % if pred & sid_p: + packet_buff[${num_header_words}] = ${XE_MACRO}(if_packet_info.sid);<% num_header_words += 1 %><% flags |= (0x1 << 28) %> + % endif ########## Class ID ########## - #if $pred & $cid_p - packet_buff[$num_header_words] = 0; //not implemented - #set $num_header_words += 1 - packet_buff[$num_header_words] = 0; //not implemented - #set $num_header_words += 1 - #set $flags |= (0x1 << 27); - #end if + % if pred & cid_p: + packet_buff[${num_header_words}] = 0; //not implemented<% num_header_words += 1 %> + packet_buff[${num_header_words}] = 0; //not implemented<% num_header_words += 1 %><% flags |= (0x1 << 27) %> + % endif ########## Integer Time ########## - #if $pred & $tsi_p - packet_buff[$num_header_words] = $(XE_MACRO)(if_packet_info.tsi); - #set $num_header_words += 1 - #set $flags |= (0x3 << 22); - #end if + % if pred & tsi_p: + packet_buff[${num_header_words}] = ${XE_MACRO}(if_packet_info.tsi);<% num_header_words += 1 %><% flags |= (0x3 << 22) %> + % endif ########## Fractional Time ########## - #if $pred & $tsf_p - packet_buff[$num_header_words] = $(XE_MACRO)(boost::uint32_t(if_packet_info.tsf >> 32)); - #set $num_header_words += 1 - packet_buff[$num_header_words] = $(XE_MACRO)(boost::uint32_t(if_packet_info.tsf >> 0)); - #set $num_header_words += 1 - #set $flags |= (0x1 << 20); - #end if + % if pred & tsf_p: + packet_buff[${num_header_words}] = ${XE_MACRO}(boost::uint32_t(if_packet_info.tsf >> 32));<% num_header_words += 1 %> + packet_buff[${num_header_words}] = ${XE_MACRO}(boost::uint32_t(if_packet_info.tsf >> 0));<% num_header_words += 1 %><% flags |= (0x1 << 20) %> + % endif ########## Burst Flags ########## - #if $pred & $eob_p - #set $flags |= (0x1 << 24); - #end if - #if $pred & $sob_p - #set $flags |= (0x1 << 25); - #end if +<% if pred & eob_p: flags |= (0x1 << 24) %><% if pred & sob_p: flags |= (0x1 << 25) %> ########## Trailer ########## - #if $pred & $tlr_p + % if pred & tlr_p: { const size_t empty_bytes = if_packet_info.num_payload_words32*sizeof(boost::uint32_t) - if_packet_info.num_payload_bytes; if_packet_info.tlr = (0x3 << 22) | (occ_table[empty_bytes & 0x3] << 10); } - packet_buff[$num_header_words+if_packet_info.num_payload_words32] = $(XE_MACRO)(if_packet_info.tlr); - #set $flags |= (0x1 << 26); - #set $num_trailer_words = 1; - #else - #set $num_trailer_words = 0; - #end if + packet_buff[${num_header_words}+if_packet_info.num_payload_words32] = ${XE_MACRO}(if_packet_info.tlr);<% flags |= (0x1 << 26) %><% num_trailer_words = 1 %> + % else: +<% num_trailer_words = 0 %> + % endif ########## Variables ########## - if_packet_info.num_header_words32 = $num_header_words; - if_packet_info.num_packet_words32 = $($num_header_words + $num_trailer_words) + if_packet_info.num_payload_words32; - vrt_hdr_flags = $hex($flags); + if_packet_info.num_header_words32 = ${num_header_words}; + if_packet_info.num_packet_words32 = ${num_header_words + num_trailer_words} + if_packet_info.num_payload_words32; + vrt_hdr_flags = ${hex(flags)}; break; - #end for + % endfor } //fill in complete header word @@ -197,9 +176,9 @@ UHD_INLINE void __if_hdr_pack_$(suffix)( } /*********************************************************************** - * interal impl of unpacking VRT IF header only + * internal impl of unpacking VRT IF header only **********************************************************************/ -UHD_INLINE void __if_hdr_unpack_$(suffix)( +UHD_INLINE void __if_hdr_unpack_${suffix}( const boost::uint32_t *packet_buff, if_packet_info_t &if_packet_info, const boost::uint32_t vrt_hdr_word32 @@ -219,86 +198,78 @@ UHD_INLINE void __if_hdr_unpack_$(suffix)( size_t empty_bytes = 0; switch(pred){ - #for $pred in range(2**7) - case $pred: - #set $has_time_spec = False - #set $num_header_words = 1 + % for pred in range(2**7): + case ${pred}:<% has_time_spec = False %><% num_header_words = 1 %> ########## Stream ID ########## - #if $pred & $sid_p + % if pred & sid_p: if_packet_info.has_sid = true; - if_packet_info.sid = $(XE_MACRO)(packet_buff[$num_header_words]); - #set $num_header_words += 1 - #else + if_packet_info.sid = ${XE_MACRO}(packet_buff[${num_header_words}]);<% num_header_words += 1 %> + % else: if_packet_info.has_sid = false; - #end if + % endif ########## Class ID ########## - #if $pred & $cid_p + % if pred & cid_p: if_packet_info.has_cid = true; - if_packet_info.cid = 0; //not implemented - #set $num_header_words += 2 - #else + if_packet_info.cid = 0; //not implemented<% num_header_words += 2 %> + % else: if_packet_info.has_cid = false; - #end if + % endif ########## Integer Time ########## - #if $pred & $tsi_p + % if pred & tsi_p: if_packet_info.has_tsi = true; - if_packet_info.tsi = $(XE_MACRO)(packet_buff[$num_header_words]); - #set $num_header_words += 1 - #else + if_packet_info.tsi = ${XE_MACRO}(packet_buff[${num_header_words}]); +<% num_header_words += 1 %> + % else: if_packet_info.has_tsi = false; - #end if + % endif ########## Fractional Time ########## - #if $pred & $tsf_p + % if pred & tsf_p: if_packet_info.has_tsf = true; - if_packet_info.tsf = boost::uint64_t($(XE_MACRO)(packet_buff[$num_header_words])) << 32; - #set $num_header_words += 1 - if_packet_info.tsf |= $(XE_MACRO)(packet_buff[$num_header_words]); - #set $num_header_words += 1 - #else + if_packet_info.tsf = boost::uint64_t(${XE_MACRO}(packet_buff[${num_header_words}])) << 32;<% num_header_words += 1 %> + if_packet_info.tsf |= ${XE_MACRO}(packet_buff[${num_header_words}]);<% num_header_words += 1 %> + % else: if_packet_info.has_tsf = false; - #end if + % endif ########## Burst Flags ########## - #if $pred & $eob_p + % if pred & eob_p: if_packet_info.eob = true; - #else + % else: if_packet_info.eob = false; - #end if - #if $pred & $sob_p + % endif + % if pred & sob_p: if_packet_info.sob = true; - #else + % else: if_packet_info.sob = false; - #end if + % endif ########## Trailer ########## - #if $pred & $tlr_p + % if pred & tlr_p: if_packet_info.has_tlr = true; - if_packet_info.tlr = $(XE_MACRO)(packet_buff[packet_words32-1]); - #set $num_trailer_words = 1; + if_packet_info.tlr = ${XE_MACRO}(packet_buff[packet_words32-1]);<% num_trailer_words = 1 %> { const int indicators = (if_packet_info.tlr >> 20) & (if_packet_info.tlr >> 8); if ((indicators & (1 << 0)) != 0) if_packet_info.eob = true; if ((indicators & (1 << 1)) != 0) if_packet_info.sob = true; empty_bytes = occ_table[(indicators >> 2) & 0x3]; } - #else - if_packet_info.has_tlr = false; - #set $num_trailer_words = 0; - #end if + % else: + if_packet_info.has_tlr = false;<% num_trailer_words = 0 %> + % endif ########## Variables ########## //another failure case - if (packet_words32 < $($num_header_words + $num_trailer_words)) + if (packet_words32 < ${num_header_words + num_trailer_words}) throw uhd::value_error("bad vrt header or invalid packet length"); - if_packet_info.num_header_words32 = $num_header_words; - if_packet_info.num_payload_words32 = packet_words32 - $($num_header_words + $num_trailer_words); + if_packet_info.num_header_words32 = ${num_header_words}; + if_packet_info.num_payload_words32 = packet_words32 - ${num_header_words + num_trailer_words}; if_packet_info.num_payload_bytes = if_packet_info.num_payload_words32*sizeof(boost::uint32_t) - empty_bytes; break; - #end for + % endfor } } /*********************************************************************** * link layer + VRT IF packing **********************************************************************/ -void vrt::if_hdr_pack_$(suffix)( +void vrt::if_hdr_pack_${suffix}( boost::uint32_t *packet_buff, if_packet_info_t &if_packet_info ){ @@ -306,29 +277,29 @@ void vrt::if_hdr_pack_$(suffix)( switch (if_packet_info.link_type) { case if_packet_info_t::LINK_TYPE_NONE: - __if_hdr_pack_$(suffix)(packet_buff, if_packet_info, vrt_hdr_word32); - packet_buff[0] = $(XE_MACRO)(vrt_hdr_word32); + __if_hdr_pack_${suffix}(packet_buff, if_packet_info, vrt_hdr_word32); + packet_buff[0] = ${XE_MACRO}(vrt_hdr_word32); break; case if_packet_info_t::LINK_TYPE_CHDR: { - __if_hdr_pack_$(suffix)(packet_buff, if_packet_info, vrt_hdr_word32); + __if_hdr_pack_${suffix}(packet_buff, if_packet_info, vrt_hdr_word32); const boost::uint32_t chdr = vrt_to_chdr(vrt_hdr_word32, if_packet_info); - packet_buff[0] = $(XE_MACRO)(chdr); + packet_buff[0] = ${XE_MACRO}(chdr); break; } case if_packet_info_t::LINK_TYPE_VRLP: - __if_hdr_pack_$(suffix)(packet_buff+2, if_packet_info, vrt_hdr_word32); + __if_hdr_pack_${suffix}(packet_buff+2, if_packet_info, vrt_hdr_word32); if_packet_info.num_header_words32 += 2; if_packet_info.num_packet_words32 += 3; - packet_buff[0] = $(XE_MACRO)(VRLP); - packet_buff[1] = $(XE_MACRO)(boost::uint32_t( + packet_buff[0] = ${XE_MACRO}(VRLP); + packet_buff[1] = ${XE_MACRO}(boost::uint32_t( (if_packet_info.num_packet_words32 & 0xfffff) | ((if_packet_info.packet_count & 0xfff) << 20) )); - packet_buff[2] = $(XE_MACRO)(vrt_hdr_word32); - packet_buff[if_packet_info.num_packet_words32-1] = $(XE_MACRO)(VEND); + packet_buff[2] = ${XE_MACRO}(vrt_hdr_word32); + packet_buff[if_packet_info.num_packet_words32-1] = ${XE_MACRO}(VEND); break; } } @@ -336,7 +307,7 @@ void vrt::if_hdr_pack_$(suffix)( /*********************************************************************** * link layer + VRT IF unpacking **********************************************************************/ -void vrt::if_hdr_unpack_$(suffix)( +void vrt::if_hdr_unpack_${suffix}( const boost::uint32_t *packet_buff, if_packet_info_t &if_packet_info ){ @@ -344,16 +315,16 @@ void vrt::if_hdr_unpack_$(suffix)( switch (if_packet_info.link_type) { case if_packet_info_t::LINK_TYPE_NONE: - vrt_hdr_word32 = $(XE_MACRO)(packet_buff[0]); - __if_hdr_unpack_$(suffix)(packet_buff, if_packet_info, vrt_hdr_word32); + vrt_hdr_word32 = ${XE_MACRO}(packet_buff[0]); + __if_hdr_unpack_${suffix}(packet_buff, if_packet_info, vrt_hdr_word32); break; case if_packet_info_t::LINK_TYPE_CHDR: { - const boost::uint32_t chdr = $(XE_MACRO)(packet_buff[0]); + const boost::uint32_t chdr = ${XE_MACRO}(packet_buff[0]); vrt_hdr_word32 = chdr_to_vrt(chdr, if_packet_info); size_t packet_count = if_packet_info.packet_count; - __if_hdr_unpack_$(suffix)(packet_buff, if_packet_info, vrt_hdr_word32); + __if_hdr_unpack_${suffix}(packet_buff, if_packet_info, vrt_hdr_word32); if_packet_info.num_payload_bytes -= (~chdr + 1) & 0x3; if_packet_info.packet_count = packet_count; break; @@ -361,12 +332,12 @@ void vrt::if_hdr_unpack_$(suffix)( case if_packet_info_t::LINK_TYPE_VRLP: { - if ($(XE_MACRO)(packet_buff[0]) != VRLP) throw uhd::value_error("bad vrl header VRLP"); - const boost::uint32_t vrl_hdr = $(XE_MACRO)(packet_buff[1]); - vrt_hdr_word32 = $(XE_MACRO)(packet_buff[2]); + if (${XE_MACRO}(packet_buff[0]) != VRLP) throw uhd::value_error("bad vrl header VRLP"); + const boost::uint32_t vrl_hdr = ${XE_MACRO}(packet_buff[1]); + vrt_hdr_word32 = ${XE_MACRO}(packet_buff[2]); if (if_packet_info.num_packet_words32 < (vrl_hdr & 0xfffff)) throw uhd::value_error("bad vrl header or packet fragment"); - if ($(XE_MACRO)(packet_buff[(vrl_hdr & 0xfffff)-1]) != VEND) throw uhd::value_error("bad vrl trailer VEND"); - __if_hdr_unpack_$(suffix)(packet_buff+2, if_packet_info, vrt_hdr_word32); + if (${XE_MACRO}(packet_buff[(vrl_hdr & 0xfffff)-1]) != VEND) throw uhd::value_error("bad vrl trailer VEND"); + __if_hdr_unpack_${suffix}(packet_buff+2, if_packet_info, vrt_hdr_word32); if_packet_info.num_header_words32 += 2; //add vrl header if_packet_info.packet_count = (vrl_hdr >> 20) & 0xfff; break; @@ -375,16 +346,16 @@ void vrt::if_hdr_unpack_$(suffix)( } ######################################################################## -#end def +</%def> ######################################################################## -$gen_code("BE_MACRO", "be") -$gen_code("LE_MACRO", "le") +${gen_code("BE_MACRO", "be")} +${gen_code("LE_MACRO", "le")} """ def parse_tmpl(_tmpl_text, **kwargs): - from Cheetah.Template import Template - return str(Template(_tmpl_text, kwargs)) + from mako.template import Template + return Template(_tmpl_text).render(**kwargs) if __name__ == '__main__': import sys |