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authorBen Hilburn <ben.hilburn@ettus.com>2014-07-17 17:57:23 -0700
committerBen Hilburn <ben.hilburn@ettus.com>2014-07-17 17:57:23 -0700
commit1af6628eb1edf29dffae771b8f3ada6952a50b69 (patch)
treefc0a9dc0f3b36397afed1cd0ec1f93e03a4c4c8e /host/lib/usrp/x300/x300_impl.hpp
parent4e8512abf885150404c2485e641d1bf02ea4ed24 (diff)
parent0753122ccaccebb15393f6496eafc94e2b1976ec (diff)
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Merge branch 'origin/ashish/rx_pcie_overflows' into maint
Diffstat (limited to 'host/lib/usrp/x300/x300_impl.hpp')
-rw-r--r--host/lib/usrp/x300/x300_impl.hpp6
1 files changed, 5 insertions, 1 deletions
diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp
index 80f3e8faa..27f20fbd9 100644
--- a/host/lib/usrp/x300/x300_impl.hpp
+++ b/host/lib/usrp/x300/x300_impl.hpp
@@ -63,7 +63,11 @@ static const size_t X300_RX_SW_BUFF_SIZE_ETH_MACOS = 0x100000; //1Mib
static const double X300_RX_SW_BUFF_FULL_FACTOR = 0.90; //Buffer should ideally be 90% full.
static const size_t X300_RX_FC_REQUEST_FREQ = 32; //per flow-control window
-static const size_t X300_PCIE_DATA_FRAME_SIZE = 8192; //bytes
+//The FIFO closest to the DMA controller is 1023 elements deep for RX and 1029 elements deep for TX
+//where an element is 8 bytes. For best throughput ensure that the data frame fits in these buffers.
+//Also ensure that the kernel has enough frames to hold buffered TX and RX data
+static const size_t X300_PCIE_RX_DATA_FRAME_SIZE = 8184; //bytes
+static const size_t X300_PCIE_TX_DATA_FRAME_SIZE = 8192; //bytes
static const size_t X300_PCIE_DATA_NUM_FRAMES = 2048;
static const size_t X300_PCIE_MSG_FRAME_SIZE = 256; //bytes
static const size_t X300_PCIE_MSG_NUM_FRAMES = 32;