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| author | Martin Braun <martin.braun@ettus.com> | 2016-12-06 12:34:22 -0800 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2016-12-08 14:30:39 -0800 |
| commit | a2e59940dcdeb7ba120339a823c34f8d31cf322e (patch) | |
| tree | 94836e8242c2bad268483cfbb6780e02034f3132 /host/lib/usrp/x300/x300_impl.cpp | |
| parent | ccd681e45937216b400f6bda326f11627a7e6def (diff) | |
| download | uhd-a2e59940dcdeb7ba120339a823c34f8d31cf322e.tar.gz uhd-a2e59940dcdeb7ba120339a823c34f8d31cf322e.tar.bz2 uhd-a2e59940dcdeb7ba120339a823c34f8d31cf322e.zip | |
x300: Make PCIe muxing and connection multi-usrp capable
Diffstat (limited to 'host/lib/usrp/x300/x300_impl.cpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp index 959245135..494598bf3 100644 --- a/host/lib/usrp/x300/x300_impl.cpp +++ b/host/lib/usrp/x300/x300_impl.cpp @@ -1025,14 +1025,14 @@ x300_impl::~x300_impl(void) } } -uint32_t x300_impl::allocate_pcie_dma_chan(const uhd::sid_t &tx_sid, const xport_type_t xport_type) +uint32_t x300_impl::mboard_members_t::allocate_pcie_dma_chan(const uhd::sid_t &tx_sid, const xport_type_t xport_type) { static const uint32_t CTRL_CHANNEL = 0; static const uint32_t FIRST_DATA_CHANNEL = 1; if (xport_type == CTRL) { return CTRL_CHANNEL; } else { - // sid_t has no comparison defined + // sid_t has no comparison defined, so we need to convert it uint32_t uint32_t raw_sid = tx_sid.get(); if (_dma_chan_pool.count(raw_sid) == 0) { @@ -1067,10 +1067,10 @@ uhd::both_xports_t x300_impl::make_transport( xports.send_sid = this->allocate_sid(mb, address, X300_SRC_ADDR0, X300_XB_DST_PCI); xports.recv_sid = xports.send_sid.reversed(); - uint32_t dma_channel_num = allocate_pcie_dma_chan(xports.send_sid, xport_type); + uint32_t dma_channel_num = mb.allocate_pcie_dma_chan(xports.send_sid, xport_type); if (xport_type == CTRL) { //Transport for control stream - if (_ctrl_dma_xport.get() == NULL) { + if (not mb.ctrl_dma_xport) { //One underlying DMA channel will handle //all control traffic zero_copy_xport_params ctrl_buff_args; @@ -1082,10 +1082,10 @@ uhd::both_xports_t x300_impl::make_transport( zero_copy_if::sptr base_xport = nirio_zero_copy::make( mb.rio_fpga_interface, dma_channel_num, ctrl_buff_args, uhd::device_addr_t()); - _ctrl_dma_xport = muxed_zero_copy_if::make(base_xport, extract_sid_from_pkt, X300_PCIE_MAX_MUXED_XPORTS); + mb.ctrl_dma_xport = muxed_zero_copy_if::make(base_xport, extract_sid_from_pkt, X300_PCIE_MAX_MUXED_XPORTS); } //Create a virtual control transport - xports.recv = _ctrl_dma_xport->make_stream(xports.recv_sid.get_dst()); + xports.recv = mb.ctrl_dma_xport->make_stream(xports.recv_sid.get_dst()); } else { //Transport for data stream default_buff_args.send_frame_size = |