bugfix#1102: Prevented X300 DAC FIFO from underflowing

- The spectral distortion was begin caused by the DAC FIFO
  underflowing. The fix was to run through the DAC sync
  procedure which uses the falling edge clock to sample
  the RefClk and sync it with the data clk

1 files changed, 3 insertions, 11 deletions

diff --git a/host/lib/usrp/x300/x300_dac_ctrl.cpp b/host/lib/usrp/x300/x300_dac_ctrl.cpp
index bb41146b6..d49fba383 100644
--- a/host/lib/usrp/x300/x300_dac_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_dac_ctrl.cpp
@@ -69,21 +69,13 @@ public:
         //ADI recommendations:
         //- soft reset the chip before configuration
         //- put the chip in sleep mode during configuration and wake it up when done
-        _soft_reset();
-        _sleep_mode(true);
-        _init();
-        _sleep_mode(false);
-    }
-
-    void reset_and_resync()
-    {
-        //ADI recommendations:
-        //- soft reset the chip before configuration
-        //- put the chip in sleep mode during configuration and wake it up when done
         //- configure synchronization settings when sleeping
         _soft_reset();
         _sleep_mode(true);
         _init();
+        //We run backend sync regardless of whether we need to sync multiple DACs
+        //because we use the internal DAC FIFO to meet system synchronous timing
+        //and we need to guarantee that the FIFO is not empty.
         _backend_sync();
         _sleep_mode(false);
     }