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author | Martin Braun <martin.braun@ettus.com> | 2018-04-16 10:56:28 -0700 |
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committer | Martin Braun <martin.braun@ettus.com> | 2018-04-17 16:48:53 -0700 |
commit | 27f5e9151c1621f25948a579c1cf7aa0e156e323 (patch) | |
tree | 18f279eacd75f24cbb833f59c9ceac17b5c1d0d4 /host/lib/usrp/x300/x300_dac_ctrl.cpp | |
parent | 6fd956def44f7315c47672e961e60a37fd5d1fca (diff) | |
download | uhd-27f5e9151c1621f25948a579c1cf7aa0e156e323.tar.gz uhd-27f5e9151c1621f25948a579c1cf7aa0e156e323.tar.bz2 uhd-27f5e9151c1621f25948a579c1cf7aa0e156e323.zip |
x300: Replace all references to boost::this_thread::sleep()
Use std::this_thread::sleep_for() instead.
Diffstat (limited to 'host/lib/usrp/x300/x300_dac_ctrl.cpp')
-rw-r--r-- | host/lib/usrp/x300/x300_dac_ctrl.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/host/lib/usrp/x300/x300_dac_ctrl.cpp b/host/lib/usrp/x300/x300_dac_ctrl.cpp index c200a696a..d7b3892fd 100644 --- a/host/lib/usrp/x300/x300_dac_ctrl.cpp +++ b/host/lib/usrp/x300/x300_dac_ctrl.cpp @@ -13,7 +13,8 @@ #include <uhd/utils/safe_call.hpp> #include <uhd/exception.hpp> #include <boost/format.hpp> -#include <boost/thread/thread.hpp> //sleep +#include <chrono> +#include <thread> #define X300_DAC_FRONTEND_SYNC_FAILURE_FATAL @@ -219,7 +220,7 @@ public: throw uhd::runtime_error("x300_dac_ctrl: timeout waiting for DAC PLL to lock"); if (reg_6 & (1 << 7)) // Lock lost? write_ad9146_reg(0x06, 0xC0); // Clear PLL event flags - boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + std::this_thread::sleep_for(std::chrono::milliseconds(10)); } } @@ -235,7 +236,7 @@ public: const time_spec_t exit_time = uhd::get_system_time() + time_spec_t(1.0); while (true) { - boost::this_thread::sleep(boost::posix_time::milliseconds(1)); // wait for sync to complete + std::this_thread::sleep_for(std::chrono::milliseconds(1)); // wait for sync to complete const size_t reg_12 = read_ad9146_reg(0x12); // Sync Status (Expect bit 7 = 0, bit 6 = 1) const size_t reg_6 = read_ad9146_reg(0x06); // Event Flags (Expect bit 5 = 0 and bit 4 = 1) if ((((reg_12 >> 6) & 0x3) == 0x1) && (((reg_6 >> 4) & 0x3) == 0x1)) |