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author | Martin Braun <martin.braun@ettus.com> | 2019-01-03 13:21:32 -0800 |
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committer | Brent Stapleton <brent.stapleton@ettus.com> | 2019-01-07 13:57:55 -0800 |
commit | f1e1a328e9a26eb956d8a2fb015d810bd04d4f96 (patch) | |
tree | f977b70255ef1394f2dd72b4222fad36635fa39a /host/lib/usrp/x300/x300_clock_ctrl.cpp | |
parent | 40bb17709182f7ce4b3761eb7e809c2be05663d2 (diff) | |
download | uhd-f1e1a328e9a26eb956d8a2fb015d810bd04d4f96.tar.gz uhd-f1e1a328e9a26eb956d8a2fb015d810bd04d4f96.tar.bz2 uhd-f1e1a328e9a26eb956d8a2fb015d810bd04d4f96.zip |
x300: Fix compiler warnings related to type conversions
These compiler warnings mostly pop up on MSVC. Most of them are due to
inconsistent usage of size_t, uint{8,16,32}_t, and even int.
This commit changes types mostly such that variables have the correct
type to begin with, although it also contains a few explicit type-casts.
Diffstat (limited to 'host/lib/usrp/x300/x300_clock_ctrl.cpp')
-rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index f5d49c97d..93e02ca7d 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -68,7 +68,7 @@ public: const double dboard_clock_rate, const double system_ref_rate): _spiface(spiface), - _slaveno(slaveno), + _slaveno(static_cast<int>(slaveno)), _hw_rev(hw_rev), _master_clock_rate(master_clock_rate), _dboard_clock_rate(dboard_clock_rate), @@ -81,10 +81,10 @@ public: _lmk04816_regs.RESET = lmk04816_regs_t::RESET_RESET; this->write_regs(0); _lmk04816_regs.RESET = lmk04816_regs_t::RESET_NO_RESET; - for (size_t i = 0; i <= 16; ++i) { + for (uint8_t i = 0; i <= 16; ++i) { this->write_regs(i); } - for (size_t i = 24; i <= 31; ++i) { + for (uint8_t i = 24; i <= 31; ++i) { this->write_regs(i); } sync_clocks(); @@ -423,8 +423,8 @@ private: // VCXO runs at 96MHz, assume PLL2 reference doubler is enabled const double ref = VCXO_FREQ * 2; - const int lowest_vcodiv = std::ceil(MIN_VCO_FREQ / output_freq); - const int highest_vcodiv = std::floor(MAX_VCO_FREQ / output_freq); + const int lowest_vcodiv = static_cast<int>(std::ceil(MIN_VCO_FREQ / output_freq)); + const int highest_vcodiv = static_cast<int>(std::floor(MAX_VCO_FREQ / output_freq)); // Find the PLL2 configuration with the lowest frequency error, favoring // higher phase comparison frequencies. @@ -445,8 +445,8 @@ private: // the N predivider to odd values as well, and we may be able to get // better spur performance by balancing the predivider and the // divider. - const int n = - boost::math::round((r * try_vco_freq) / (VCXO_PLL2_N * ref)); + const int n = static_cast<int>( + boost::math::round((r * try_vco_freq) / (VCXO_PLL2_N * ref))); const double actual_mcr = (ref * VCXO_PLL2_N * n) / (vcodiv * r); const double error = std::abs(actual_mcr - output_freq); @@ -869,10 +869,10 @@ private: set_clock_delay(X300_CLOCK_WHICH_DAC0, _delays.dac_dly_ns, false); //Sets both Ch0 and Ch1 /* Write the configuration values into the LMK */ - for (size_t i = 1; i <= 16; ++i) { + for (uint8_t i = 1; i <= 16; ++i) { this->write_regs(i); } - for (size_t i = 24; i <= 31; ++i) { + for (uint8_t i = 24; i <= 31; ++i) { this->write_regs(i); } @@ -880,7 +880,7 @@ private: } const spi_iface::sptr _spiface; - const size_t _slaveno; + const int _slaveno; const size_t _hw_rev; // This is technically constant, but it can be coerced during initialization double _master_clock_rate; |