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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-08-20 09:06:32 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-08-20 09:06:32 -0700 |
| commit | 72eae0503393966dfb2b961835ad1f9c5e5265e7 (patch) | |
| tree | 60db7af4b572f280f3017b8ba3a5f39657c58816 /host/lib/usrp/x300/x300_clock_ctrl.cpp | |
| parent | 505c1d84fa7c53c0c640fab73b88c164671c7b91 (diff) | |
| parent | d31ffb2ef869b05fc4aeafd6bf588e62dca7ee82 (diff) | |
| download | uhd-72eae0503393966dfb2b961835ad1f9c5e5265e7.tar.gz uhd-72eae0503393966dfb2b961835ad1f9c5e5265e7.tar.bz2 uhd-72eae0503393966dfb2b961835ad1f9c5e5265e7.zip | |
Merge branch 'master' into ashish/cat_refactor_phase2
Diffstat (limited to 'host/lib/usrp/x300/x300_clock_ctrl.cpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index a8b30a0ab..da97dd2cf 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -283,6 +283,7 @@ void set_master_clock_rate(double clock_rate) { _lmk04816_regs.CLKout0_1_PD = lmk04816_regs_t::CLKOUT0_1_PD_POWER_UP; this->write_regs(0); _lmk04816_regs.CLKout0_1_DIV = vco_div; + _lmk04816_regs.CLKout0_ADLY_SEL = lmk04816_regs_t::CLKOUT0_ADLY_SEL_D_EV_X; this->write_regs(0); // Register 1 @@ -294,6 +295,8 @@ void set_master_clock_rate(double clock_rate) { // Register 3 _lmk04816_regs.CLKout6_7_DIV = vco_div; _lmk04816_regs.CLKout6_7_OSCin_Sel = lmk04816_regs_t::CLKOUT6_7_OSCIN_SEL_VCO; + _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_EV_X; + _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_EV_X; // Register 4 _lmk04816_regs.CLKout8_9_DIV = vco_div; // Register 5 @@ -305,12 +308,20 @@ void set_master_clock_rate(double clock_rate) { _lmk04816_regs.CLKout1_TYPE = lmk04816_regs_t::CLKOUT1_TYPE_P_DOWN; //CPRI feedback clock, use LVDS _lmk04816_regs.CLKout2_TYPE = lmk04816_regs_t::CLKOUT2_TYPE_LVPECL_700MVPP; //DB_0_RX _lmk04816_regs.CLKout3_TYPE = lmk04816_regs_t::CLKOUT3_TYPE_LVPECL_700MVPP; //DB_1_RX + // Analog delay of 900ps to synchronize the radio clock with the source synchronous ADC clocks. + // This delay may need to vary due to temperature. Tested and verified at room temperature only. + _lmk04816_regs.CLKout0_1_ADLY = 0x10; + // Register 7 _lmk04816_regs.CLKout4_TYPE = lmk04816_regs_t::CLKOUT4_TYPE_LVPECL_700MVPP; //DB_1_TX _lmk04816_regs.CLKout5_TYPE = lmk04816_regs_t::CLKOUT5_TYPE_LVPECL_700MVPP; //DB_0_TX _lmk04816_regs.CLKout6_TYPE = lmk04816_regs_t::CLKOUT6_TYPE_LVPECL_700MVPP; //DB0_DAC _lmk04816_regs.CLKout7_TYPE = lmk04816_regs_t::CLKOUT7_TYPE_LVPECL_700MVPP; //DB1_DAC _lmk04816_regs.CLKout8_TYPE = lmk04816_regs_t::CLKOUT8_TYPE_LVPECL_700MVPP; //DB0_ADC + // Analog delay of 900ps to synchronize the DAC reference clocks with the source synchronous DAC clocks. + // This delay may need to vary due to temperature. Tested and verified at room temperature only. + _lmk04816_regs.CLKout6_7_ADLY = 0x10; + // Register 8 _lmk04816_regs.CLKout9_TYPE = lmk04816_regs_t::CLKOUT9_TYPE_LVPECL_700MVPP; //DB1_ADC _lmk04816_regs.CLKout10_TYPE = lmk04816_regs_t::CLKOUT10_TYPE_LVDS; //REF_CLKOUT |