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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-03-15 20:43:51 -0700 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-03-15 20:43:51 -0700 |
| commit | 4726c0c0958c776bccdf9898384e335013c7e811 (patch) | |
| tree | 08c179bc422238013574108b56b5a29d73280cd9 /host/lib/usrp/x300/x300_clock_ctrl.cpp | |
| parent | 4022711d4ffc1b05780e5e4c4bd2bb176fb41c95 (diff) | |
| parent | 9126069560de0a462f58596055dad15b35693dce (diff) | |
| download | uhd-4726c0c0958c776bccdf9898384e335013c7e811.tar.gz uhd-4726c0c0958c776bccdf9898384e335013c7e811.tar.bz2 uhd-4726c0c0958c776bccdf9898384e335013c7e811.zip | |
Merge clock and PPS fixes.
Diffstat (limited to 'host/lib/usrp/x300/x300_clock_ctrl.cpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index a986928a7..a8b30a0ab 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -48,6 +48,10 @@ x300_clock_ctrl_impl(uhd::spi_iface::sptr spiface, set_master_clock_rate(master_clock_rate); } +void reset_clocks() { + set_master_clock_rate(_master_clock_rate); +} + void sync_clocks(void) { //soft sync: //put the sync IO into output mode - FPGA must be input |