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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-07-07 14:57:25 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-07-07 15:15:17 -0700 |
| commit | cf3566e750000fcc125a4d192c975d0100655483 (patch) | |
| tree | c07ef8e4bbfd546b0bbad2ada9a21c55814f2ed8 /host/lib/usrp/x300/x300_adc_ctrl.cpp | |
| parent | e840a3ca30ae136a3c0886b005645a03656ec64c (diff) | |
| download | uhd-cf3566e750000fcc125a4d192c975d0100655483.tar.gz uhd-cf3566e750000fcc125a4d192c975d0100655483.tar.bz2 uhd-cf3566e750000fcc125a4d192c975d0100655483.zip | |
x300: Added self-cal to tune ADC source-sync data delays
- Self-calibration routine steps through various values of IDELAY
taps on the SS data bits to detect metastability in the capture interface
and computes an ideal delay tap value
- Self calibration is triggered at device creation
Diffstat (limited to 'host/lib/usrp/x300/x300_adc_ctrl.cpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_adc_ctrl.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/usrp/x300/x300_adc_ctrl.cpp b/host/lib/usrp/x300/x300_adc_ctrl.cpp index b0e4e4b95..edb4ce885 100644 --- a/host/lib/usrp/x300/x300_adc_ctrl.cpp +++ b/host/lib/usrp/x300/x300_adc_ctrl.cpp @@ -55,8 +55,8 @@ public: _ads62p48_regs.lvds_cmos = ads62p48_regs_t::LVDS_CMOS_DDR_LVDS; _ads62p48_regs.channel_control = ads62p48_regs_t::CHANNEL_CONTROL_INDEPENDENT; _ads62p48_regs.data_format = ads62p48_regs_t::DATA_FORMAT_2S_COMPLIMENT; - _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_MINUS7_26; - _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_MINUS7_26; + _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_NORMAL; + _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_NORMAL; this->send_ads62p48_reg(0); |